| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 207 unsigned SubReg1; in isProfitableToTransform() local
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
348 SubReg1 = 0; in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
|
| H A D | AArch64ISelLowering.cpp | 17154 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode() local
17155 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
17201 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
17203 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
17204 SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
215 SubReg0 = SubReg1; in commuteInstructionImpl()
233 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1844 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1845 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1855 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1856 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1866 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1867 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1877 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1878 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1892 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
1907 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode()
[all …]
|
| H A D | ARMISelLowering.cpp | 10041 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
10042 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 846 SDValue RC, SubReg0, SubReg1; in Select() local
851 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
855 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
860 N->getOperand(1), SubReg1 }; in Select()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1172 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
1183 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
1215 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
|