| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned SubReg0; in isProfitableToTransform() local
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
342 SubReg0 = 0; in transformInstruction()
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
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| H A D | AArch64ISelLowering.cpp | 17153 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); in createGPRPairNode() local
17155 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
210 SubReg0 = SubReg2; in commuteInstructionImpl()
215 SubReg0 = SubReg1; in commuteInstructionImpl()
229 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1843 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
1845 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1854 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode() local
1856 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1865 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode() local
1867 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1876 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode() local
1878 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1892 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
1907 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode()
[all …]
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| H A D | ARMISelLowering.cpp | 10040 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
10042 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 846 SDValue RC, SubReg0, SubReg1; in Select() local
850 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); in Select()
854 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
859 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, in Select()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 140 unsigned RegClassID, unsigned SubReg0) { in createTupleImpl() argument
150 Ops.push_back(CurDAG.getTargetConstant(SubReg0 + I, DL, MVT::i32)); in createTupleImpl()
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