| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 245 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /freebsd-13.1/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 213 const llvm::APSInt &Sub1(const llvm::APSInt &V) { in Sub1() function
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1089 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
1094 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
1099 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
1132 Sub1, in SelectADD_SUB_I64()
1792 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl() local
1797 DL, MVT::i32, N0, Sub1); in SelectFlatOffsetImpl()
1814 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
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| H A D | AMDGPULegalizerInfo.cpp | 3013 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
3070 Sel2, Sub1); in legalizeUnsignedDIV_REM64Impl()
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| H A D | AMDGPUISelLowering.cpp | 1935 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1986 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 436 const MCInst *Sub1 = MI.getOperand(1).getInst(); in EncodeSingleInstruction() local
442 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); in EncodeSingleInstruction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 438 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| H A D | HexagonConstPropagation.cpp | 1957 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate() local
1962 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1966 assert(Sub1 != Sub2); in evaluate()
1967 bool LoIs1 = (Sub1 == SubLo); in evaluate()
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| /freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1351 auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1, in computeComposites()
1354 const RegMap &Img1 = SubRegAction.at(Sub1); in computeComposites()
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| /freebsd-13.1/contrib/googletest/googletest/docs/ |
| H A D | advanced.md | 966 10: void Sub1(int n) {
975 19: Sub1(1);
978 22: Sub1(9);
999 `Sub1()` the two failures come from respectively. (You could add
1001 an extra message to each assertion in `Sub1()` to indicate the value of `n`, but
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5817 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
5821 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8340 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, in expandFixedPointDiv() local
8344 Sub1, Quot); in expandFixedPointDiv()
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| H A D | DAGCombiner.cpp | 20199 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); in narrowInsertExtractVectorBinOp() local
20204 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
20210 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, in narrowInsertExtractVectorBinOp()
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