Searched refs:SrcVT0 (Results 1 – 1 of 1) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 37608 EVT SrcVT0 = Src0.getValueType(); in canonicalizeLaneShuffleWithRepeatedOps() local
37611 if (!Src1.isUndef() && (SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1)) in canonicalizeLaneShuffleWithRepeatedOps()
37619 DAG.getNode(X86ISD::VPERM2X128, DL, SrcVT0, LHS, RHS, V.getOperand(2)); in canonicalizeLaneShuffleWithRepeatedOps()
37620 Res = DAG.getNode(SrcOpc0, DL, SrcVT0, Res); in canonicalizeLaneShuffleWithRepeatedOps()
37625 if (SrcVT0 == MVT::v4f64) { in canonicalizeLaneShuffleWithRepeatedOps()
37638 SDValue Res = DAG.getNode(X86ISD::VPERM2X128, DL, SrcVT0, LHS, RHS, in canonicalizeLaneShuffleWithRepeatedOps()
37640 Res = DAG.getNode(SrcOpc0, DL, SrcVT0, Res, Src0.getOperand(1)); in canonicalizeLaneShuffleWithRepeatedOps()
50173 EVT SrcVT0 = Src0.getOperand(0).getValueType(); in combineConcatVectorOps() local
50175 unsigned NumSrcElts0 = SrcVT0.getVectorNumElements(); in combineConcatVectorOps()
50177 if (SrcVT0.is256BitVector() && SrcVT1.is256BitVector() && in combineConcatVectorOps()
|