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Searched refs:Src0VT (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP3Instructions.td19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
36 dag src0_dag = (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers));
63 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
72 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))];
81 …(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
87 …(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
88 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
92 … (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))];
[all …]
H A DSIInstrInfo.td2001 !if(!eq(Src0VT.Size, 64),
2018 !if(!eq(Src0VT.Size, 64),
2082 field ValueType Src0VT = ArgVT[1];
2100 field Operand Src0ModDPP = getSrcModDPP<Src0VT>.ret;
2102 field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
2111 field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
2116 field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
2121 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
2133 field bit IsPacked = isPackedType<Src0VT>.ret;
2138 field bit HasModifiers = !or(isModifierType<Src0VT>.ret,
[all …]
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
103 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
105 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
107 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOPCInstructions.td69 let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
93 let ReadsModeReg = isFloatType<P.Src0VT>.ret;
194 (setcc (P.Src0VT
196 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
197 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
200 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
658 (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers)),
H A DVOPInstructions.td124 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
511 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
642 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
787 !subst(P.Src0RC32, P.Src0VT,
H A DVOP2Instructions.td72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
125 (node (P.Src0VT
127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
596 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
605 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2265 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
2275 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
2288 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()