Searched refs:SplitVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6615 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements); in LowerVSETCC() local
6616 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0); in LowerVSETCC()
6617 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1); in LowerVSETCC()
6618 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1, in LowerVSETCC()
6620 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
6621 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed); in LowerVSETCC()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 19516 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), in reduceBuildVecToShuffle() local
19518 if (TLI.isTypeLegal(SplitVT) && in reduceBuildVecToShuffle()
19519 SplitSize + SplitVT.getVectorNumElements() <= in reduceBuildVecToShuffle()
19521 SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, in reduceBuildVecToShuffle()
19523 SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, in reduceBuildVecToShuffle()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7797 EVT SplitVT = in LowerTRUNCATEVector() local
7799 unsigned SplitNumElts = SplitVT.getVectorNumElements(); in LowerTRUNCATEVector()
7800 Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
7802 Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 15739 MVT SplitVT = MVT::getVectorVT(ScalarVT, SplitNumElements); in splitAndLowerShuffle() local
15746 return std::make_pair(DAG.getBitcast(SplitVT, LoV), in splitAndLowerShuffle()
15747 DAG.getBitcast(SplitVT, HiV)); in splitAndLowerShuffle()
15785 return DAG.getUNDEF(SplitVT); in splitAndLowerShuffle()
15787 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask); in splitAndLowerShuffle()
15789 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask); in splitAndLowerShuffle()
15794 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask); in splitAndLowerShuffle()
15804 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask); in splitAndLowerShuffle()
15812 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask); in splitAndLowerShuffle()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11960 EVT SplitVT = in LowerSVEStructLoad() local
11963 assert(isTypeLegal(SplitVT)); in LowerSVEStructLoad()
11965 SmallVector<EVT, 5> VTs(N, SplitVT); in LowerSVEStructLoad()
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