Searched refs:ShiftedVal (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 134 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros; in generateInstSeq() local
138 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros); in generateInstSeq()
141 generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq); in generateInstSeq()
153 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros); in generateInstSeq()
155 generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq); in generateInstSeq()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 213 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
215 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
216 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3977 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
3981 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3982 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3985 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
3988 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
3989 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
3990 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
3994 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4001 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
4002 if (!CanShrinkImmediate(ShiftedVal)) in tryShrinkShlLogicImm()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 930 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
931 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
943 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
944 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1693 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1694 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1695 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1708 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1709 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1710 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12705 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine() local
12708 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0; in performMulCombine()
12709 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal; in performMulCombine()
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