Searched refs:ShiftWidth (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.h | 50 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
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| H A D | RISCVISelDAGToDAG.cpp | 1435 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, in selectShiftMask() argument
1445 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); in selectShiftMask()
1446 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2343 unsigned ShiftWidth = TypeSize - 1;
2356 auto LHS = m_AShr(m_Value(OpL), m_SpecificInt(ShiftWidth));
2357 auto RHS = m_LShr(m_Neg(m_Value(OpR)), m_SpecificInt(ShiftWidth));
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1212 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1222 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); in isSVEDataVectorRegWithShiftExtend()
1225 !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8) in isSVEDataVectorRegWithShiftExtend()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1622 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16)); in applyMappingBFE() local
1627 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth); in applyMappingBFE()
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