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Searched refs:ShiftVal (Results 1 – 24 of 24) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp274 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
275 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
278 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
295 ShiftVal = 12; in getAddSubImmOpValue()
297 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
553 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
554 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
559 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
580 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
581 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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H A DAArch64InstPrinter.cpp1081 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1093 if (ShiftVal != 0) in printArithExtend()
1094 O << ", lsl #" << ShiftVal; in printArithExtend()
1099 if (ShiftVal != 0) in printArithExtend()
1100 O << " #" << ShiftVal; in printArithExtend()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp198 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
199 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h258 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
259 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
273 unsigned &ShiftVal);
274 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1877 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
1949 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
1950 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
1958 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2248 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
2249 return ShiftVal >= Size / 2 && ShiftVal < Size; in matchCombineShiftToUnmerge()
2259 assert(ShiftVal >= HalfSize); in applyCombineShiftToUnmerge()
2265 unsigned NarrowShiftAmt = ShiftVal - HalfSize; in applyCombineShiftToUnmerge()
2301 if (ShiftVal == HalfSize) { in applyCombineShiftToUnmerge()
2305 } else if (ShiftVal == Size - 1) { in applyCombineShiftToUnmerge()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1234 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1239 ShiftVal, SetFlags, WantResult); in emitAddSub()
1256 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1262 ShiftVal, SetFlags, WantResult); in emitAddSub()
1618 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
4582 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4610 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4645 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
4676 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4679 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
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H A DAArch64TargetTransformInfo.cpp79 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
80 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
H A DAArch64ISelDAGToDAG.cpp515 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
516 if (ShiftVal > 3) in isWorthFoldingSHL()
801 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
808 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
809 if (ShiftVal > 4) in SelectArithExtendedRegister()
837 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
1051 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
1053 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
H A DAArch64InstrInfo.cpp895 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
896 if (ShiftVal == 0) in isFalkorShiftExtFast()
898 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
922 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
923 return ShiftVal == 0 || in isFalkorShiftExtFast()
924 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
930 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
931 return ShiftVal == 0 || in isFalkorShiftExtFast()
932 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp784 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
785 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2113 auto ShiftVal = DAG.getSplatValue(Op.getOperand(1)); in LowerShift() local
2114 if (!ShiftVal) in LowerShift()
2118 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2135 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2372 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2381 ShiftVal = Amount; in isSimpleShift()
2530 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2533 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2534 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2535 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2541 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2544 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2545 (MaskVal << ShiftVal != 0) && in adjustForTestUnderMask()
2546 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal && in adjustForTestUnderMask()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp389 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
390 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
396 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86TargetTransformInfo.cpp4337 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
4338 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
H A DX86ISelLowering.cpp7837 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
18876 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
18887 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
35072 if (ShiftVal.uge(VTBits)) in ComputeNumSignBitsForTargetNode()
35075 if (ShiftVal.uge(Tmp)) in ComputeNumSignBitsForTargetNode()
35083 if (ShiftVal.uge(VTBits - 1)) in ComputeNumSignBitsForTargetNode()
35086 ShiftVal += Tmp; in ComputeNumSignBitsForTargetNode()
35087 return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBitsForTargetNode()
44195 ShiftVal = NumBitsPerElt - 1; in combineVectorShiftImm()
44199 if (!ShiftVal) in combineVectorShiftImm()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp506 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
509 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
516 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2086 const APInt *ShiftVal; in foldICmpShlConstant() local
2087 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2088 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
2234 const APInt *ShiftVal; in foldICmpShrConstant() local
2235 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal))) in foldICmpShrConstant()
2236 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal); in foldICmpShrConstant()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2253 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2260 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
2275 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2276 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2282 And.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
H A DAMDGPUISelLowering.cpp4175 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
4177 BitsFrom, ShiftVal); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1165 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
1174 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
1178 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
1183 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
1184 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
1193 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5900 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
5903 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
5991 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
6008 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
6009 if (ShiftVal > 4) in selectArithExtendedRegister()
6045 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1990 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2006 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp13438 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
13443 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
13444 ShiftVal -= 16; in EmitX86BuiltinExpr()
13453 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
13475 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
13479 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
13564 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
13594 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
13622 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
13644 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp2450 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
2452 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
2455 if (Known.countMinTrailingZeros() >= ShiftVal) in isKnownNonZero()