| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 773 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
774 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
775 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 810 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
815 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
818 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
836 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
881 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
882 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
3812 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
3817 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
3818 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
3820 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| H A D | DAGCombiner.cpp | 2219 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
2221 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2225 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2230 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2231 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
7175 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
7176 if (!ShiftOp) in calculateByteProvider()
7179 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
7997 auto matchFirstShift = [&](SDValue V, SDValue &ShiftOp, in combineShiftOfShiftedLogic()
8007 ShiftOp = V.getOperand(0); in combineShiftOfShiftedLogic()
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| H A D | SelectionDAGBuilder.cpp | 2815 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2824 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2830 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2835 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1904 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1905 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3341 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3386 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7201 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
7204 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 217 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
221 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
222 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
223 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
225 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
45347 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
45348 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
45352 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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