Home
last modified time | relevance | path

Searched refs:ShiftBits (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp92 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getVecExtParmsType() local
103 XCOFF::TracebackTable::ParmTypeIsVectorCharBit >> ShiftBits; in getVecExtParmsType()
109 XCOFF::TracebackTable::ParmTypeIsVectorShortBit >> ShiftBits; in getVecExtParmsType()
115 XCOFF::TracebackTable::ParmTypeIsVectorIntBit >> ShiftBits; in getVecExtParmsType()
121 XCOFF::TracebackTable::ParmTypeIsVectorFloatBit >> ShiftBits; in getVecExtParmsType()
137 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getParmsType() local
151 XCOFF::TracebackTable::ParmTypeIsFixedBits >> ShiftBits; in getParmsType()
163 XCOFF::TracebackTable::ParmTypeIsFloatingBits >> ShiftBits; in getParmsType()
170 XCOFF::TracebackTable::ParmTypeIsDoubleBits >> ShiftBits; in getParmsType()
180 XCOFF::TracebackTable::ParmTypeIsVectorBits >> ShiftBits; in getParmsType()
H A DPPCRegisterInfo.cpp925 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
928 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
1087 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
1092 .addImm(ShiftBits ? 32 - ShiftBits : 0) in lowerCRBitRestore()
1093 .addImm(ShiftBits) in lowerCRBitRestore()
1094 .addImm(ShiftBits); in lowerCRBitRestore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp404 unsigned ShiftBits = Offset.getBitWidth() - PointerSize; in adjustToPointerSize() local
405 return (Offset << ShiftBits).ashr(ShiftBits); in adjustToPointerSize()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4144 unsigned ShiftBits = AndRHSC.countTrailingZeros(); in SimplifySetCC() local
4145 if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
4148 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
4149 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); in SimplifySetCC()
4161 unsigned ShiftBits; in SimplifySetCC() local
4165 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
4169 ShiftBits = C1.countTrailingZeros(); in SimplifySetCC()
4171 NewC.lshrInPlace(ShiftBits); in SimplifySetCC()
4172 if (ShiftBits && NewC.getMinSignedBits() <= 64 && in SimplifySetCC()
4174 !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
[all …]
H A DDAGCombiner.cpp5177 unsigned ShiftBits = CShift->getZExtValue(); in visitANDLike() local
5180 if (ShiftBits == 0) in visitANDLike()
5189 (ShiftBits + MaskBits <= Size / 2) && in visitANDLike()
5209 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT); in visitANDLike()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4698 unsigned ShiftBits = countLeadingZeros(Mask); in getARMCmp() local
4699 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) { in getARMCmp()
4700 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32); in getARMCmp()
4702 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32); in getARMCmp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6192 SDValue ShiftBits = DAG.getTargetConstant(SubVecNumElems, dl, MVT::i8); in insert1BitVector() local
6195 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6196 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6244 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8); in insert1BitVector() local
6245 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
6246 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()