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Searched refs:ShiftAmount (Results 1 – 25 of 31) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp104 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeqImpl() local
105 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in generateInstSeqImpl()
109 if (ShiftAmount > 12 && !isInt<12>(Hi52) && isInt<32>((uint64_t)Hi52 << 12)) { in generateInstSeqImpl()
111 ShiftAmount -= 12; in generateInstSeqImpl()
117 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRShiftExpand.cpp92 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
96 Value *Cmp1 = Builder.CreateICmpEQ(ShiftAmount, Int8Zero); in expand()
103 ShiftAmountPHI->addIncoming(ShiftAmount, BB); in expand()
H A DAVRISelLowering.cpp321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
344 ShiftAmount -= 4; in LowerShifts()
351 ShiftAmount -= 4; in LowerShifts()
356 ShiftAmount = 0; in LowerShifts()
361 ShiftAmount = 0; in LowerShifts()
366 ShiftAmount = 0; in LowerShifts()
369 if (4 <= ShiftAmount && ShiftAmount < 8) in LowerShifts()
374 ShiftAmount -= 4; in LowerShifts()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp277 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second); in eliminateFrameIndex() local
278 if (ShiftAmount != 0) in eliminateFrameIndex()
281 .addImm(ShiftAmount); in eliminateFrameIndex()
H A DRISCVInstrInfo.cpp1486 uint32_t ShiftAmount = Log2_32(NumOfVReg); in getVLENFactoredAmount() local
1487 if (ShiftAmount == 0) in getVLENFactoredAmount()
1491 .addImm(ShiftAmount) in getVLENFactoredAmount()
1495 uint32_t ShiftAmount = Log2_32(NumOfVReg - 1); in getVLENFactoredAmount() local
1498 .addImm(ShiftAmount) in getVLENFactoredAmount()
1506 uint32_t ShiftAmount = Log2_32(NumOfVReg + 1); in getVLENFactoredAmount() local
1509 .addImm(ShiftAmount) in getVLENFactoredAmount()
H A DRISCVFrameLowering.cpp509 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
514 .addImm(ShiftAmount) in emitPrologue()
518 .addImm(ShiftAmount) in emitPrologue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h48 unsigned ShiftAmount) const;
H A DMipsTargetStreamer.h145 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
H A DMipsSEISelDAGToDAG.cpp283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp268 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
270 if (ShiftAmount >= 32) { in emitDSLL()
271 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
275 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
H A DMipsMCCodeEmitter.h188 template <unsigned ShiftAmount = 0>
H A DMipsMCCodeEmitter.cpp753 template <unsigned ShiftAmount>
764 OffBits >>= ShiftAmount; in getMemEncoding()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp967 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
972 if (ShiftAmount >= 8) { in LowerShifts()
992 ShiftAmount -= 8; in LowerShifts()
995 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
999 ShiftAmount -= 1; in LowerShifts()
1002 while (ShiftAmount--) in LowerShifts()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp411 unsigned ShiftAmount; member
583 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
901 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1985 unsigned ShiftAmount = 0, in CreateReg() argument
1993 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
2004 unsigned ShiftAmount = 0, in CreateVectorReg() argument
2093 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
3024 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
3026 if (ShiftAmount < 0) { in tryParseImmWithOptionalShift()
3033 if (ShiftAmount == 0 && Imm != nullptr) { in tryParseImmWithOptionalShift()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1004 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
1009 ShiftAmount)); in instCombineIntrinsic()
1049 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
1053 ShiftAmount)); in instCombineIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1044 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1046 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1047 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
H A DTargetLowering.cpp6365 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
6367 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { in expandMUL_LOHI()
6373 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); in expandMUL_LOHI()
7366 SDValue ShiftAmount = in scalarizeVectorLoad() local
7369 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
7451 SDValue ShiftAmount = in scalarizeVectorStore() local
7454 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
7628 SDValue ShiftAmount = in expandUnalignedLoad() local
7631 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
7742 SDValue ShiftAmount = DAG.getConstant( in expandUnalignedStore() local
[all …]
H A DLegalizeIntegerTypes.cpp827 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); in PromoteIntRes_ADDSUBSHLSAT() local
829 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
832 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
836 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
3529 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX() local
3531 ShiftAmount); in ExpandIntRes_MULFIX()
3533 ShiftAmount); in ExpandIntRes_MULFIX()
H A DLegalizeDAG.cpp1590 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
1597 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1598 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1600 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1601 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp6731 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6733 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6737 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
6740 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
6752 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6754 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6755 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
6769 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
6770 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
6774 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1857 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1858 if (ShiftAmount == Power) in factorOutPowerOf2()
1860 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp516 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
518 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
529 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp460 unsigned &ShiftAmount);
5255 const MCExpr *ShiftAmount; in parsePKHImm() local
5258 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
5262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
5338 const MCExpr *ShiftAmount; in parseShifterImm() local
5340 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
5344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
5400 const MCExpr *ShiftAmount; in parseRotImm() local
5402 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
5406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2426 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
2460 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
2461 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
2468 if (ShlImm - ShiftAmount != 0 && !BiggerPattern) in isBitfieldPositioningOp()
2470 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1338 template <unsigned Bits, unsigned ShiftAmount = 0>
1346 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1350 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
2814 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
2815 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; in loadImmediate()
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()

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