Searched refs:Shift2 (Results 1 – 10 of 10) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 462 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64() local
464 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 66 MachineInstr *Shift2; member
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1890 MatchInfo.Shift2 = LogicMIOp1; in matchShiftOfShiftedLogic()
1893 MatchInfo.Shift2 = LogicMIOp2; in matchShiftOfShiftedLogic()
1921 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
1926 Register Shift2 = Builder in applyShiftOfShiftedLogic() local
1932 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
1935 MatchInfo.Shift2->eraseFromParent(); in applyShiftOfShiftedLogic()
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/ObjectYAML/ |
| H A D | ELFYAML.h | 424 llvm::yaml::Hex32 Shift2; member
|
| /freebsd-13.1/contrib/llvm-project/lld/ELF/ |
| H A D | SyntheticSections.h | 686 enum { Shift2 = 26 }; enumerator
|
| H A D | SyntheticSections.cpp | 2412 write32(buf + 12, Shift2); in writeTo()
2436 val |= uint64_t(1) << ((sym.hash >> Shift2) % c); in writeBloomFilter()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | ELFYAML.cpp | 1727 IO.mapRequired("Shift2", E.Shift2); in mapping()
|
| H A D | ELFEmitter.cpp | 1746 CBA.write<uint32_t>(Section.Header->Shift2, ELFT::TargetEndianness); in writeSectionContent()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5354 def Shift2 {
5360 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5361 (AND Shift2.Left, MaskValues.Hi2));
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28550 SDValue Shift2 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
28552 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
43314 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
43316 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
|