| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
|
| H A D | X86ISelLowering.cpp | 25636 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
25641 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
25647 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
30045 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerADDSUBCARRY()
42388 SDValue SetCC; in checkBoolTestSetCCCombine() local
42394 SetCC = Op2; in checkBoolTestSetCCCombine()
42396 SetCC = Op1; in checkBoolTestSetCCCombine()
42420 SetCC = SetCC.getOperand(OpIdx); in checkBoolTestSetCCCombine()
42423 SetCC = SetCC.getOperand(0); in checkBoolTestSetCCCombine()
47509 return SetCC; in combineXor()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 680 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
682 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
683 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
707 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
710 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
711 SetCC.getOperand(1), in performSELECTCombine()
714 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
737 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
745 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
746 SetCC.getOperand(1), in performSELECTCombine()
[all …]
|
| H A D | MipsSEISelLowering.cpp | 985 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
991 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
|
| H A D | MipsInstrInfo.td | 1515 // SetCC
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrPrefix.td | 2443 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2445 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2447 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2449 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2451 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2469 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2471 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2473 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2475 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2479 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
[all …]
|
| H A D | PPCInstrInfo.td | 4125 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
4129 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
4133 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
4135 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
4138 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
4140 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
4142 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),
4144 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
4146 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
4148 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
[all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1402 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO() local
1406 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
1937 SDValue SetCC = in LowerSETCC() local
1941 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
1942 return SetCC; in LowerSETCC()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2190 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
7819 SDValue SetCC = in visitXOR() local
7822 CombineTo(N, SetCC); in visitXOR()
10543 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
10554 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
10555 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
10759 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
10886 SDValue SetCC = N->getOperand(0); in foldExtendedSignBitTest() local
10888 !SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) in foldExtendedSignBitTest()
10891 SDValue X = SetCC.getOperand(0); in foldExtendedSignBitTest()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1089 SDValue SetCC; in PromoteIntRes_SETCC() local
1094 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers); in PromoteIntRes_SETCC()
1097 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1099 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1103 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
|
| H A D | TargetLowering.cpp | 8377 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO() local
8378 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
8399 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
8400 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
|
| H A D | SelectionDAGBuilder.cpp | 7150 SDValue SetCC = DAG.getSetCC(DL, CCVT, VectorInduction.getValue(0), in visitIntrinsicCall() local
7154 SetCC)); in visitIntrinsicCall()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4771 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
4774 return SetCC; in lowerICMPIntrinsic()
4775 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
4801 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
4804 return SetCC; in lowerFCMPIntrinsic()
4805 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
5044 SDNode *SetCC = nullptr; in LowerBRCOND() local
5048 SetCC = Intr; in LowerBRCOND()
5049 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
5067 assert(!SetCC || in LowerBRCOND()
[all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3749 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
3751 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
3753 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
3815 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerADDSUBCARRY() local
3817 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
3819 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1964 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
1969 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15903 SDValue SetCC = N->getOperand(0); in performVSelectCombine() local
15904 if (SetCC.getOpcode() == ISD::SETCC && in performVSelectCombine()
15905 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
15906 SDValue CmpLHS = SetCC.getOperand(0); in performVSelectCombine()
15908 SDNode *CmpRHS = SetCC.getOperand(1).getNode(); in performVSelectCombine()
15947 SetCC = DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(), in performVSelectCombine()
15950 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
16010 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine() local
16014 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask); in performSelectCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5851 for (SDNode *SetCC : SetCCs) { in performANY_EXTENDCombine()
5855 SDValue SOp = SetCC->getOperand(j); in performANY_EXTENDCombine()
5862 Ops.push_back(SetCC->getOperand(2)); in performANY_EXTENDCombine()
5863 DCI.CombineTo(SetCC, in performANY_EXTENDCombine()
5864 DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in performANY_EXTENDCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 12762 SDValue SetCC; in PerformSELECTCombine() local
12771 SetCC = N->getOperand(0); in PerformSELECTCombine()
12772 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
12773 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
12774 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()
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