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Searched refs:STG (Results 1 – 18 of 18) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td68 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, R8, SpLim
72 // Pass in STG registers: F1, ..., F6
75 // Pass in STG registers: D1, ..., D6
78 // Pass in STG registers: XMM1, ..., XMM6
H A DSystemZFrameLowering.cpp515 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG)) in emitPrologue()
710 BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::STG)) in inlineStackProbe()
H A DSystemZInstrInfo.cpp1119 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD; in foldMemoryOperandImpl()
1340 splitMove(MI, SystemZ::STG); in expandPostRAPseudo()
1589 StoreOpcode = SystemZ::STG; in getLoadStoreOpcodes()
H A DSystemZScheduleZ196.td192 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZEC12.td200 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ13.td220 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ15.td222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ14.td221 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZISelLowering.cpp8312 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false); in EmitInstrWithCustomInserter()
8314 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true); in EmitInstrWithCustomInserter()
H A DSystemZInstrInfo.td484 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp74 const unsigned OpCode1 = ZeroData ? AArch64ISD::STZG : AArch64ISD::STG; in EmitUnrolledSetTag()
H A DAArch64CallingConvention.td343 // which defines the registers for the Spineless Tagless G-Machine (STG) that
344 // GHC uses to implement lazy evaluation. The generic STG machine has a set of
348 // The STG Machine is documented here:
370 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
H A DAArch64ISelLowering.h437 STG, enumerator
H A DAArch64InstrInfo.td601 def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemO…
1834 defm STG : MemTagStore<0b00, "stg">;
1871 // Large STG to be expanded into a loop. $sz is the size, $Rn is start address.
H A DAArch64ISelLowering.cpp2097 MAKE_CASE(AArch64ISD::STG) in getTargetNodeName()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td696 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
700 // Pass in STG registers: F1, F2, F3, F4, D1, D2
986 // Pass in STG registers: Base, Sp, Hp, R1
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
/freebsd-13.1/share/misc/
H A Dpci_vendors6310 0008 STG 2000X
6311 0009 STG 1764X
6335 1746 STG 1764X
27036 15d9 0734 AOC-STG-I2T