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Searched refs:SRsrc (Results 1 – 3 of 3) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp193 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
196 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
205 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
1559 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1655 SDValue &SRsrc, in SelectMUBUFScratchOffset() argument
1666 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffset()
1690 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffset()
1716 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
2453 SDValue SRsrc, VAddr, SOffset, Offset; in SelectATOMIC_CMP_SWAP() local
2463 SDValue Ops[] = {CmpVal, VAddr, SRsrc, SOffset, Offset, CPol, in SelectATOMIC_CMP_SWAP()
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H A DSILoadStoreOptimizer.cpp87 bool SRsrc = false; member
433 Result.SRsrc = true; in getRegs()
448 Result.SRsrc = true; in getRegs()
459 Result.SRsrc = true; in getRegs()
548 if (Regs.SRsrc) in setMI()
H A DSIInstrInfo.cpp5271 Register SRsrc = MRI.createVirtualRegister(SRsrcRC); in emitLoadSRsrcFromVGPRLoop() local
5274 auto Merge = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc); in emitLoadSRsrcFromVGPRLoop()
5282 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
5574 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local
5575 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands()
5576 CreatedBB = loadSRsrcFromVGPR(*this, MI, *SRsrc, MDT); in legalizeOperands()