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Searched refs:SPLAT_VECTOR (Results 1 – 20 of 20) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp98 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
165 setOperationAction(ISD::SPLAT_VECTOR, T, Custom); in initializeHVXLowering()
269 setTargetDAGCombine(ISD::SPLAT_VECTOR); in initializeHVXLowering()
531 SDValue S = DAG.getNode(ISD::SPLAT_VECTOR, dl, WordTy, SplatV); in buildHvxVectorReg()
1162 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1458 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1460 SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1462 SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
2092 case ISD::SPLAT_VECTOR: in LowerHvxOperation()
2256 if (Ops[0].getOpcode() == ISD::SPLAT_VECTOR) { in PerformHvxDAGCombine()
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H A DHexagonISelLowering.cpp1653 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1712 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2325 case ISD::SPLAT_VECTOR: in getVectorShiftByInt()
2448 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2509 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2727 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h590 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h833 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp142 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
314 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicate()
347 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
2476 case ISD::SPLAT_VECTOR: in isSplatValue()
2614 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
5286 else if (N1->getOpcode() == ISD::SPLAT_VECTOR) in FoldConstantArithmetic()
5330 assert((N1->getOpcode() == ISD::SPLAT_VECTOR || in FoldConstantArithmetic()
5404 Op.getOpcode() != ISD::SPLAT_VECTOR) { in FoldConstantVectorArithmetic()
9582 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstOrConstSplat()
9645 if (N.getOpcode() == ISD::SPLAT_VECTOR) in isConstOrConstSplatFP()
[all …]
H A DSelectionDAGDumper.cpp294 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DLegalizeVectorOps.cpp936 : ISD::SPLAT_VECTOR, in ExpandSELECT()
H A DLegalizeVectorTypes.cpp928 case ISD::SPLAT_VECTOR: in SplitVectorResult()
1665 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
1680 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode"); in SplitVecRes_ScalarOp()
2991 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DLegalizeIntegerTypes.cpp114 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1501 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
4253 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
4859 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op); in PromoteIntRes_SPLAT_VECTOR()
H A DTargetLowering.cpp5079 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
5197 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
5354 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
5623 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareUREMEqFold()
5882 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DDAGCombiner.cpp970 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
8619 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
10053 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
10107 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
10109 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
18746 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
19776 if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) in visitBUILD_VECTOR()
19779 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
H A DLegalizeDAG.cpp3725 case ISD::SPLAT_VECTOR: in ExpandNode()
H A DSelectionDAGBuilder.cpp3561 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1513 if (N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplat()
1527 if ((N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplatSimmHelper()
1576 if ((N.getOpcode() != ISD::SPLAT_VECTOR && in selectVSplatUimm5()
H A DRISCVISelLowering.cpp455 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
494 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
587 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
716 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
2509 case ISD::SPLAT_VECTOR: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1168 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1213 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1266 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1305 setOperationAction(ISD::SPLAT_VECTOR, MVT::nxv8bf16, Custom); in AArch64TargetLowering()
1570 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in addTypeForFixedLengthSVE()
4250 if (Splat.getOpcode() != ISD::SPLAT_VECTOR) in getGatherScatterIndexIsExtended()
4829 case ISD::SPLAT_VECTOR: in LowerOperation()
9592 SDValue SplatOne = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, One); in LowerDUPQLane()
14147 Comparator.getOpcode() == ISD::SPLAT_VECTOR) { in tryConvertSVEWideCompare()
14195 SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, DL, CmpVT, Imm); in tryConvertSVEWideCompare()
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H A DAArch64ISelDAGToDAG.cpp167 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
187 case ISD::SPLAT_VECTOR: { in SelectDupZero()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp839 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); in initActions()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td668 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4549 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()