Home
last modified time | relevance | path

Searched refs:SMLAL (Results 1 – 12 of 12) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h265 SMLAL, // 64bit Signed Accumulate Multiply enumerator
H A DARMInstrInfo.td4387 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4419 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4572 // Halfword multiply accumulate long: SMLAL<x><y>.
4573 class SMLAL<bits<2> opc1, string asm>
4582 def SMLALBB : SMLAL<0b00, "smlalbb">;
4583 def SMLALBT : SMLAL<0b10, "smlalbt">;
4584 def SMLALTB : SMLAL<0b01, "smlaltb">;
4585 def SMLALTT : SMLAL<0b11, "smlaltt">;
6375 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6386 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMScheduleSwift.td307 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleR52.td279 "SMLAL", "UMLAL", "SMLALBT",
H A DARMISelDAGToDAG.cpp3928 case ARMISD::SMLAL:{ in Select()
3942 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMISelLowering.cpp1763 MAKE_CASE(ARMISD::SMLAL) in getTargetNodeName()
12437 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in AddCombineTo64BitSMLAL16() local
12440 SDValue HiMLALResult(SMLAL.getNode(), 1); in AddCombineTo64BitSMLAL16()
12441 SDValue LoMLALResult(SMLAL.getNode(), 0); in AddCombineTo64BitSMLAL16()
12530 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
12580 FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) && in AddCombineTo64bitMLAL()
H A DARMInstrFormats.td1007 // SMLAL*
H A DARMInstrThumb2.td3150 // Halfword multiple accumulate long: SMLAL<x><y>
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td526 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td4946 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
5050 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
6231 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8268 case ARM::SMLAL: in validateInstruction()