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Searched refs:SLTu (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
320 SLTu = Mips::SLTu_MM; in expandAtomicBinOpSubword()
332 SLTu = Mips::SLTu; in expandAtomicBinOpSubword()
457 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
594 SLTu = Mips::SLTu_MM; in expandAtomicBinOp()
609 SLTu = Mips::SLTu; in expandAtomicBinOp()
624 SLTu = Mips::SLTu64; in expandAtomicBinOp()
743 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
H A DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
H A DMipsInstructionSelector.cpp770 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); in select()
773 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); in select()
776 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); in select()
780 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); in select()
783 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); in select()
H A DMipsFastISel.cpp660 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
664 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
667 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
671 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
677 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
H A DMipsInstrInfo.td2064 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,
2742 (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2745 (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3277 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3330 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>, ISA_MIPS1;
3331 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3332 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3333 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
H A DMipsScheduleP5600.td225 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
H A DMipsScheduleGeneric.td50 SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4143 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4551 OpCode = Mips::SLTu; in expandSge()
4588 OpRegCode = Mips::SLTu; in expandSgeImm()
4644 OpCode = Mips::SLTu; in expandSgtImm()
4688 OpCode = Mips::SLTu; in expandSle()
4724 OpRegCode = Mips::SLTu; in expandSleImm()
4801 FinalOpcode = Mips::SLTu; in expandAliasImmediate()
5456 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5461 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5481 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
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