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Searched refs:SINT_TO_FP (Results 1 – 25 of 35) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp611 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
697 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
699 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
701 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
703 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
705 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
707 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
709 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
711 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
713 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp172 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
299 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
1037 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5845 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
5847 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
5865 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
9345 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
9346 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
10137 case ISD::SINT_TO_FP: in LowerOperation()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1570 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
1571 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
1673 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
1674 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1675 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
1676 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
1677 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
1678 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp851 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
1831 setOperationAction(ISD::SINT_TO_FP, VT, in X86TargetLowering()
2044 setTargetDAGCombine(ISD::SINT_TO_FP); in X86TargetLowering()
19779 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP_AVX512DQ()
19821 case ISD::SINT_TO_FP: in useVectorCast()
20078 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext); in LowerSINT_TO_FP()
31058 case ISD::SINT_TO_FP: in ReplaceNodeResults()
49139 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
49179 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineSIntToFP()
50705 if (InOpcode == ISD::SINT_TO_FP && in combineExtractSubvector()
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H A DX86IntrinsicsInfo.h913 X86_INTRINSIC_DATA(avx512_sitofp_round, INTR_TYPE_1OP, ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp991 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
992 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
993 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
999 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1000 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1001 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1007 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
1008 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1014 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1023 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp462 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
463 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
464 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
888 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
1159 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1225 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1567 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
4868 case ISD::SINT_TO_FP: in LowerOperation()
12940 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
16614 case ISD::SINT_TO_FP: in PerformDAGCombine()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h739 SINT_TO_FP, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp476 case ISD::SINT_TO_FP: in LegalizeOp()
576 case ISD::SINT_TO_FP: in Promote()
1259 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1322 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1324 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1003 case ISD::SINT_TO_FP: in LegalizeOp()
2284 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2414 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2437 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2502 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
2915 case ISD::SINT_TO_FP: in ExpandNode()
4043 SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, SDLoc(Node), in ConvertNodeToLibcall()
4153 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
4157 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP || in ConvertNodeToLibcall()
4365 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp136 case ISD::SINT_TO_FP: in SoftenFloatResult()
757 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1252 case ISD::SINT_TO_FP: in ExpandFloatResult()
1650 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2273 case ISD::SINT_TO_FP: in PromoteFloatResult()
2636 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp348 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DLegalizeVectorTypes.cpp104 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
613 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
998 case ISD::SINT_TO_FP: in SplitVectorResult()
2186 case ISD::SINT_TO_FP: in SplitVectorOperand()
3098 case ISD::SINT_TO_FP: in WidenVectorResult()
4565 case ISD::SINT_TO_FP: in WidenVectorOperand()
H A DFastISel.cpp313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1794 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DSelectionDAG.cpp4375 case ISD::SINT_TO_FP: in isKnownNeverNaN()
4677 case ISD::SINT_TO_FP: { in getNode()
4681 Opcode==ISD::SINT_TO_FP, in getNode()
4821 case ISD::SINT_TO_FP: in getNode()
4878 case ISD::SINT_TO_FP: in getNode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp165 setTargetDAGCombine(ISD::SINT_TO_FP); in WebAssemblyTargetLowering()
241 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
2240 case ISD::SINT_TO_FP: in performVectorConvertLowCombine()
2268 case ISD::SINT_TO_FP: in performVectorConvertLowCombine()
2311 case ISD::SINT_TO_FP: in performVectorConvertLowCombine()
2473 case ISD::SINT_TO_FP: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp244 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
492 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
1318 setTargetDAGCombine(ISD::SINT_TO_FP); in PPCTargetLowering()
8297 if (UI->getOpcode() != ISD::SINT_TO_FP && in directMoveIsProfitable()
8310 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in convertIntToFP()
8346 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FPDirectMove()
8436 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FP()
14055 if (FirstInput.getOpcode() != ISD::SINT_TO_FP && in DAGCombineBuildVector()
14097 assert((N->getOpcode() == ISD::SINT_TO_FP || in combineFPToIntToFP()
14123 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in combineFPToIntToFP()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1514 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1516 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3032 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3382 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3389 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp442 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
476 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
1304 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1734 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2551 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2613 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1776 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1777 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1778 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp411 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
412 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
431 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
432 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
650 setTargetDAGCombine(ISD::SINT_TO_FP); in SystemZTargetLowering()
6746 case ISD::SINT_TO_FP: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1812 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp478 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
514 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
698 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
2381 case ISD::SINT_TO_FP: in LowerOperation()
2456 case ISD::SINT_TO_FP: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp358 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); in addMSAIntType()
1875 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()

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