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Searched refs:SIEncodingFamily (Results 1 – 14 of 14) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td30 SIMCInstr <NAME, SIEncodingFamily.NONE> {
56 : EXP_Real<_done, pseudo, SIEncodingFamily.SI>, EXPe {
70 : EXP_Real<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
84 : EXP_Real<_done, pseudo, SIEncodingFamily.GFX10>, EXPe {
H A DVOP2Instructions.td927 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
957 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
963 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
1281 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1286 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1409 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1415 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1421 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1427 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1457 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
[all …]
H A DVOP3Instructions.td820 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
825 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
840 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
845 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
952 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
957 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
980 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
985 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1065 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
1080 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
[all …]
H A DVOP1Instructions.td522 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10> {
548 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
553 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
558 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
622 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
627 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
653 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
658 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
745 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
753 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
[all …]
H A DVOP3PInstructions.td503 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
512 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
525 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
528 …def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90…
535 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
652 def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
H A DVOPInstructions.td48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
493 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> {
527 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
592 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
601 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>;
628 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
H A DSIInstrInfo.td20 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
21 def SIEncodingFamily {
2341 SIMCInstr<opName, SIEncodingFamily.NONE> {
2358 SIMCInstr<opName, SIEncodingFamily.VI> {
2449 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2450 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2451 [!cast<string>(SIEncodingFamily.VI)],
2452 [!cast<string>(SIEncodingFamily.SDWA)],
2453 [!cast<string>(SIEncodingFamily.SDWA9)],
2458 [!cast<string>(SIEncodingFamily.GFX80)],
[all …]
H A DVOPCInstructions.td79 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
886 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
889 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
909 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
916 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
1003 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
1006 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1232 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1236 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
H A DBUFInstructions.td66 SIMCInstr<opName, SIEncodingFamily.NONE> {
303 SIMCInstr<opName, SIEncodingFamily.NONE> {
1909 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
1915 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
2230 Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.SI> {
2291 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.VI, has_sccb> {
2300 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX90A, has_sccb> {
2363 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
2527 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.VI> {
2535 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.GFX90A> {
[all …]
H A DSMInstructions.td27 SIMCInstr<opName, SIEncodingFamily.NONE> {
456 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
509 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
731 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
887 SM_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10>, Enc64 {
H A DDSInstructions.td11 SIMCInstr <opName, SIEncodingFamily.NONE> {
998 SIEncodingFamily.GFX10>;
1025 SIEncodingFamily.SI>;
1048 SIEncodingFamily.SI>;
1194 SIMCInstr <ps.Mnemonic, SIEncodingFamily.VI> {
H A DSIInstrInfo.cpp7540 enum SIEncodingFamily { enum
7558 return SIEncodingFamily::SI; in subtargetEncodingFamily()
7561 return SIEncodingFamily::VI; in subtargetEncodingFamily()
7563 return SIEncodingFamily::GFX10; in subtargetEncodingFamily()
7589 SIEncodingFamily Gen = subtargetEncodingFamily(ST); in pseudoToMCOpcode()
7593 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
7599 Gen = SIEncodingFamily::GFX80; in pseudoToMCOpcode()
7604 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
7607 Gen = SIEncodingFamily::SDWA9; in pseudoToMCOpcode()
7610 Gen = SIEncodingFamily::SDWA10; in pseudoToMCOpcode()
[all …]
H A DSOPInstructions.td25 SIMCInstr<opName, SIEncodingFamily.NONE> {
700 SIMCInstr<opName, SIEncodingFamily.NONE> {
1457 class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
1462 class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
1467 class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
H A DFLATInstructions.td23 SIMCInstr<opName, SIEncodingFamily.NONE> {
1325 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
1393 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
1569 FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {