Home
last modified time | relevance | path

Searched refs:RegisterFiles (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp119 SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles()); in dispatch() local
121 PRF.addRegisterWrite(WriteRef(IR.getSourceIndex(), &WS), RegisterFiles); in dispatch()
130 notifyInstructionDispatched(IR, RegisterFiles, in dispatch()
148 SmallVector<unsigned, 8> RegisterFiles(PRF.getNumRegisterFiles(), 0U); in cycleStart() local
149 notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes); in cycleStart()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp77 RegisterFiles.emplace_back(NumRegs); in initialize()
88 const MCRegisterFileDesc &RF = Info.RegisterFiles[I]; in initialize()
101 for (RegisterMappingTracker &RMT : RegisterFiles) in cycleStart()
154 unsigned RegisterFileIndex = RegisterFiles.size(); in addRegisterFile()
203 RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex]; in allocatePhysRegs()
209 RegisterFiles[0].NumUsedPhysRegs += Cost; in allocatePhysRegs()
218 RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex]; in freePhysRegs()
224 RegisterFiles[0].NumUsedPhysRegs -= Cost; in freePhysRegs()
429 RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex]; in tryEliminateMoveOrSwap()
665 const RegisterMappingTracker &RMT = RegisterFiles[I]; in isAvailable()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h135 SmallVector<RegisterMappingTracker, 4> RegisterFiles; variable
293 unsigned getNumRegisterFiles() const { return RegisterFiles.size(); } in getNumRegisterFiles()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h183 const MCRegisterFileDesc *RegisterFiles; member
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DRegisterFileStatistics.cpp126 const MCRegisterFileDesc &RFDesc = PI.RegisterFiles[I]; in printView()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.h247 std::vector<CodeGenRegisterFile> RegisterFiles; member
271 !RegisterFiles.empty(); in hasExtraProcessorInfo()
H A DSubtargetEmitter.cpp676 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { in EmitRegisterFileTables()
687 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
712 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
761 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), in EmitExtraProcessorInfo()
H A DCodeGenSchedule.cpp1840 PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(),RF)); in collectRegisterFiles()
1841 CodeGenRegisterFile &CGRF = PM.RegisterFiles.back(); in collectRegisterFiles()