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Searched refs:RegisterClasses (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp136 if (!RegisterClasses.empty()) { in runEnums()
139 assert(RegisterClasses.size() <= 0xffff && in runEnums()
146 for (const auto &RC : RegisterClasses) in runEnums()
1041 for (const auto &RC : RegisterClasses) { in runMCDesc()
1078 for (const auto &RC : RegisterClasses) { in runMCDesc()
1186 if (!RegisterClasses.empty()) { in runTargetHeader()
1190 for (const auto &RC : RegisterClasses) { in runTargetHeader()
1227 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1273 if (!RegisterClasses.empty()) { in runTargetDesc()
1434 for (const auto &RC : RegisterClasses) in runTargetDesc()
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H A DInstrInfoEmitter.cpp350 std::vector<Record *> RegisterClasses = in emitOperandTypeMappings() local
362 {&Operands, &RegisterOperands, &RegisterClasses}) { in emitOperandTypeMappings()
H A DAsmMatcherEmitter.cpp730 RegisterClassesTy RegisterClasses; member in __anon1f497f8e0111::AsmMatcherInfo
1326 RegisterClasses[It.first] = RegisterSetClasses[It.second]; in buildRegisterClasses()
1330 ClassInfo *CI = RegisterClasses[Rec]; in buildRegisterClasses()
1575 Op.Class = RegisterClasses[RegRecord]; in buildInfo()
2490 for (const auto &RC : Info.RegisterClasses) in emitValidateOperandClass()
H A DCodeGenSchedule.cpp1855 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); in collectRegisterFiles() local
1858 for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) { in collectRegisterFiles()
1867 CGRF.Costs.emplace_back(RegisterClasses[I], Cost, AllowMoveElim); in collectRegisterFiles()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td14 list<RegisterClass> RegisterClasses = classes;