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Searched refs:RegType (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td5657 [(set (AccumType RegType:$dst),
5658 (OpNode (AccumType RegType:$Rd),
5659 (InputType RegType:$Rn),
5679 [(set (AccumType RegType:$dst),
7910 …: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:…
7933 RegType, RegType, V128, VectorIndexS,
7935 [(set (AccumType RegType:$dst),
8046 BaseSIMDIndexedTied<Q, U, 0b0, size, {0b111, Mixed}, RegType, RegType, V128,
8048 [(set (AccumType RegType:$dst),
8073 BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
[all …]
H A DAArch64FrameLowering.cpp2223 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enum
H A DAArch64InstrInfo.td900 string rhs_kind, RegisterOperand RegType,
903 lhs_kind, rhs_kind, RegType, AccumType,
905 let Pattern = [(set (AccumType RegType:$dst),
906 (AccumType (int_aarch64_neon_usdot (AccumType RegType:$Rd),
910 (InputType RegType:$Rn))))];
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7000 MVT RegType = TLI->getRegisterType(Context, OldVT); in optimizeSwitchInst() local
7001 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
7020 if (TLI->isSExtCheaperThanZExt(OldVT, RegType)) in optimizeSwitchInst()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td223 // RegType - Specify the list ValueType of the registers in this register