| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.h | 52 const char* getRegClassName(unsigned RegClassID) const;
55 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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| H A D | AMDGPUDisassembler.cpp | 816 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
818 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
837 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
839 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
841 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1613 switch (RegClassID) { in GetSIDIForRegClass()
1647 int RegClassID = -1; in VerifyAndAdjustOperands() local
1668 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1675 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1677 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1679 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1686 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
4838 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, in parseSEHRegisterNumber() argument
4849 if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) { in parseSEHRegisterNumber()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| H A D | AArch64RegisterInfo.td | 655 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
885 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
937 # RegClassSuffix # "RegClassID>";
976 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1153 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1286 # EltSize # ", AArch64::" # RC # "RegClassID>";
1312 # EltSize # ", AArch64::" # RC # "RegClassID>";
1347 # EltSize # ", AArch64::" # RC # "RegClassID>";
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 141 void SelectBuildVector(SDNode *N, unsigned RegClassID);
713 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
718 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
735 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
840 unsigned RegClassID = in Select() local
842 SelectBuildVector(N, RegClassID); in Select()
3164 unsigned RegClassID; in Select() local
3170 case 2: RegClassID = R600::R600_Reg64RegClassID; break; in Select()
3173 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
3175 RegClassID = R600::R600_Reg128RegClassID; in Select()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 906 unsigned RegClassID; in convertVRToVRMx() local
908 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
910 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
912 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
916 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 140 unsigned RegClassID, unsigned SubReg0) { in createTupleImpl() argument
146 Ops.push_back(CurDAG.getTargetConstant(RegClassID, DL, MVT::i32)); in createTupleImpl()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1952 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1960 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1275 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1277 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1280 template <unsigned RegClassID, int ExtWidth>
1285 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 1843 template<unsigned Bits, unsigned RegClassID>
1846 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()
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