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Searched refs:Reg2 (Results 1 – 25 of 32) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp651 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
670 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
682 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && in generateCompactUnwindEncoding()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2181 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
2185 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
2312 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2318 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2502 MIB.addReg(RPI.Reg2); in spillCalleeSavedRegisters()
2516 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
2572 std::swap(Reg1, Reg2); in spillCalleeSavedRegisters()
2580 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
2581 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
2624 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp199 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
202 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
212 MIB.addReg(Reg2) in emitStore()
222 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
225 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
235 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp876 unsigned Reg2) { in EmitInstrRegReg() argument
885 Reg1 = Reg2; in EmitInstrRegReg()
886 Reg2 = Temp; in EmitInstrRegReg()
890 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
900 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
907 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
911 Reg1 = Reg2; in EmitMovFPIntPair()
912 Reg2 = temp; in EmitMovFPIntPair()
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
H A DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
H A DMipsTargetStreamer.h134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp1101 Register Reg1, Reg2; in parseAddress() local
1147 if (parseAddressRegister(Reg2)) in parseAddress()
1149 Base = Regs[Reg2.Num]; in parseAddress()
1155 if (parseAddressRegister(Reg2)) in parseAddress()
1157 Base = Regs[Reg2.Num]; in parseAddress()
1179 if (parseAddressRegister(Reg2)) in parseAddress()
1181 Base = Regs[Reg2.Num]; in parseAddress()
1193 if (parseAddressRegister(Reg2)) in parseAddress()
1195 Base = Regs[Reg2.Num]; in parseAddress()
1465 Register Reg1, Reg2; in parseOperand() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
H A DPPCVSXSwapRemoval.cpp897 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
898 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp186 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
201 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl()
209 Reg0 = Reg2; in commuteInstructionImpl()
211 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
232 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
245 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
H A DAggressiveAntiDepBreaker.cpp89 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
95 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h100 bool contains(Register Reg1, Register Reg2) const { in contains() argument
103 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
105 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp760 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
763 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
765 if (Reg0 != Reg2) { in ReduceTo2Addr()
795 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
796 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
H A DA15SDOptimizer.cpp83 unsigned Reg2);
448 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
456 .addReg(Reg2) in createRegSequence()
H A DARMFastISel.cpp2794 unsigned Reg2 = 0; in SelectShift() local
2796 Reg2 = getRegForValue(Src2Value); in SelectShift()
2797 if (Reg2 == 0) return false; in SelectShift()
2810 MIB.addReg(Reg2); in SelectShift()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp221 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
227 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
233 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
79 return contains(Reg1) && contains(Reg2); in contains()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1300 unsigned Reg2 = Instr.getRegister2(); in emitCFIInstruction() local
1303 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); in emitCFIInstruction()
1307 Streamer.emitULEB128IntValue(Reg2); in emitCFIInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1762 StringRef Reg2(R2); in processInstruction() local
1766 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1906 StringRef Reg2(R2); in processInstruction() local
1910 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1399 CodeGenRegister *Reg2 = I1.second; in computeComposites() local
1401 if (&Reg1 == Reg2) in computeComposites()
1403 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1409 if (Reg2 == Reg3) in computeComposites()

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