Home
last modified time | relevance | path

Searched refs:Reduction (Results 1 – 21 of 21) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp54 class Reduction;
85 class Reduction { class
93 Reduction() = delete;
95 Reduction (Instruction *Add) : Root(Add) { } in Reduction() function in __anon6435b0bd0111::Reduction
225 bool Search(Value *V, BasicBlock *BB, Reduction &R);
227 void InsertParallelMACs(Reduction &Reduction);
230 bool CreateParallelPairs(Reduction &R);
432 bool ARMParallelDSP::Search(Value *V, BasicBlock *BB, Reduction &R) { in Search()
525 Reduction R(&I); in MatchSMLAD()
544 bool ARMParallelDSP::CreateParallelPairs(Reduction &R) { in CreateParallelPairs()
[all …]
H A DARMISelLowering.cpp12850 auto Reduction = in PerformSELECTCombine() local
12855 Reduction = DCI.DAG.getNode(ISD::TRUNCATE, dl, VectorScalarType, Reduction); in PerformSELECTCombine()
12857 return Reduction; in PerformSELECTCombine()
H A DARMInstrMVE.td947 def SDTVecReduceR : SDTypeProfile<1, 2, [ // Reduction of an integer and vector into an integer
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVScheduleV.td203 // 14. Vector Reduction Operations
204 // 14.1. Vector Single-Width Integer Reduction Instructions
206 // 14.2. Vector Widening Integer Reduction Instructions
208 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
211 // 14.4. Vector Widening Floating-Point Reduction Instructions
416 // 14. Vector Reduction Operations
417 // 14.1. Vector Single-Width Integer Reduction Instructions
420 // 14.2. Vector Widening Integer Reduction Instructions
428 // 14.4. Vector Widening Floating-Point Reduction Instructions
628 // 15. Vector Reduction Operations
[all …]
H A DRISCV.td111 "'Zbr' (Polynomial Reduction 'B' Instructions)">;
114 "'Zbr' (Polynomial Reduction 'B' Instructions)">;
H A DRISCVInstrInfoVPseudos.td3765 // 15.1. Vector Single-Width Integer Reduction Instructions
3777 // 15.2. Vector Widening Integer Reduction Instructions
3785 // 15.3. Vector Single-Width Floating-Point Reduction Instructions
3793 // 15.4. Vector Widening Floating-Point Reduction Instructions
4430 // 15.1. Vector Single-Width Integer Reduction Instructions
4442 // 15.2. Vector Widening Integer Reduction Instructions
4450 // 15.3. Vector Single-Width Floating-Point Reduction Instructions
4458 // 15.4. Vector Widening Floating-Point Reduction Instructions
H A DRISCVInstrInfoV.td1304 // Vector Single-Width Integer Reduction Instructions
1316 // Vector Widening Integer Reduction Instructions
1329 // Vector Single-Width Floating-Point Reduction Instructions
1337 // Vector Widening Floating-Point Reduction Instructions
H A DRISCVInstrInfoVVLPatterns.td928 // 15.1. Vector Single-Width Integer Reduction Instructions
940 // 15.3. Vector Single-Width Floating-Point Reduction Instructions
H A DRISCVISelLowering.cpp3836 SDValue Reduction = in lowerVECREDUCE() local
3838 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction, in lowerVECREDUCE()
3895 SDValue Reduction = in lowerFPVECREDUCE() local
3897 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction, in lowerFPVECREDUCE()
/freebsd-13.1/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.txt1 QCOM CPR (Core Power Reduction)
3 CPR (Core Power Reduction) is a technology to reduce core power on a CPU
/freebsd-13.1/usr.sbin/lpr/filters.ru/
H A Dbjc-240.sh.sample55 Reduction=Off
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp924 return (all_of(getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeFPMath() argument
925 const RecurrenceDescriptor &RdxDesc = Reduction.second; in canVectorizeFPMath()
1257 for (auto &Reduction : getReductionVars()) in prepareToFoldTailByMasking() local
1258 ReductionLiveOuts.insert(Reduction.second.getLoopExitInstr()); in prepareToFoldTailByMasking()
H A DLoopVectorize.cpp7921 for (auto &Reduction : Legal->getReductionVars()) { in collectValuesToIgnore() local
7922 RecurrenceDescriptor &RedDes = Reduction.second; in collectValuesToIgnore()
7936 for (auto &Reduction : Legal->getReductionVars()) { in collectInLoopReductions() local
7937 PHINode *Phi = Reduction.first; in collectInLoopReductions()
7938 RecurrenceDescriptor &RdxDesc = Reduction.second; in collectInLoopReductions()
9176 for (auto &Reduction : CM.getInLoopReductionChains()) { in buildVPlanWithVPRecipes() local
9177 PHINode *Phi = Reduction.first; in buildVPlanWithVPRecipes()
9429 for (auto &Reduction : Legal->getReductionVars()) { in buildVPlanWithVPRecipes() local
9430 if (CM.isInLoopReduction(Reduction.first)) in buildVPlanWithVPRecipes()
9498 for (auto &Reduction : CM.getInLoopReductionChains()) { in adjustRecipesForInLoopReductions() local
[all …]
/freebsd-13.1/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_mve.td539 multiclass Reduction<Type Accumulator, string basename, list<Type> basetypes,
561 defm vminvq: Reduction<Scalar, "minv", [Vector], 1, (seq (Scalar $ret))>;
562 defm vmaxvq: Reduction<Scalar, "maxv", [Vector], 1, (seq (Scalar $ret))>;
566 defm vminavq: Reduction<UScalar, "minav", [Vector], 0, (seq (UScalar $ret))>;
567 defm vmaxavq: Reduction<UScalar, "maxav", [Vector], 0, (seq (UScalar $ret))>;
571 defm vminnmvq: Reduction<Scalar, "minnmv", [Scalar, Vector]>;
572 defm vmaxnmvq: Reduction<Scalar, "maxnmv", [Scalar, Vector]>;
573 defm vminnmavq: Reduction<Scalar, "minnmav", [Scalar, Vector]>;
574 defm vmaxnmavq: Reduction<Scalar, "maxnmav", [Scalar, Vector]>;
H A Driscv_vector.td1868 // 15. Vector Reduction Operations
1869 // 15.1. Vector Single-Width Integer Reduction Instructions
1879 // 15.2. Vector Widening Integer Reduction Instructions
1880 // Vector Widening Integer Reduction Operations
1888 // 15.3. Vector Single-Width Floating-Point Reduction Instructions
1894 // 15.4. Vector Widening Floating-Point Reduction Instructions
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td544 // For Reduction ternary operations.
552 // For Reduction ternary operations with mask.
H A DIntrinsics.td1610 //===------------------------ Reduction Intrinsics ------------------------===//
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td1306 // Section 8.14 - Vector Reduction Instructions
1366 // Section 8.14.7 - VRAND (Vector Reduction And)
1369 // Section 8.14.8 - VROR (Vector Reduction Or)
1372 // Section 8.14.9 - VRXOR (Vector Reduction Exclusive Or)
/freebsd-13.1/contrib/byacc/
H A Dbtyaccpar.skel1048 /* Reduction declares that this path is valid. Set yypath and do a full parse */
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntime.cpp624 std::pair<llvm::Function *, llvm::Function *> Reduction = in emitInitWithReductionInitializer() local
640 RValue Func = RValue::get(Reduction.second); in emitInitWithReductionInitializer()
5416 std::pair<llvm::Function *, llvm::Function *> Reduction = in emitReductionCombiner() local
5418 RValue Func = RValue::get(Reduction.first); in emitReductionCombiner()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td4780 // SVE Floating Point Fast Reduction Group
4816 // SVE Floating Point Accumulating Reduction Group
7548 // SVE Integer Reduction Group