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Searched refs:ReadAdvance (Results 1 – 25 of 50) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td177 def : ReadAdvance<ReadJmp, 0>;
178 def : ReadAdvance<ReadJalr, 0>;
179 def : ReadAdvance<ReadCSR, 0>;
182 def : ReadAdvance<ReadIALU, 0>;
183 def : ReadAdvance<ReadIALU32, 0>;
188 def : ReadAdvance<ReadIDiv, 0>;
189 def : ReadAdvance<ReadIDiv32, 0>;
190 def : ReadAdvance<ReadIMul, 0>;
191 def : ReadAdvance<ReadIMul32, 0>;
204 def : ReadAdvance<ReadFMA32, 0>;
[all …]
H A DRISCVSchedSiFive7.td165 def : ReadAdvance<ReadJmp, 0>;
166 def : ReadAdvance<ReadJalr, 0>;
167 def : ReadAdvance<ReadCSR, 0>;
170 def : ReadAdvance<ReadIALU, 0>;
171 def : ReadAdvance<ReadIALU32, 0>;
176 def : ReadAdvance<ReadIDiv, 0>;
177 def : ReadAdvance<ReadIDiv32, 0>;
178 def : ReadAdvance<ReadIMul, 0>;
179 def : ReadAdvance<ReadIMul32, 0>;
192 def : ReadAdvance<ReadFMA32, 0>;
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H A DRISCVScheduleV.td663 def : ReadAdvance<ReadVLDX, 0>;
664 def : ReadAdvance<ReadVSTX, 0>;
669 def : ReadAdvance<ReadVSTM, 0>;
670 def : ReadAdvance<ReadVLDSX, 0>;
671 def : ReadAdvance<ReadVSTSX, 0>;
696 def : ReadAdvance<ReadVST1R, 0>;
697 def : ReadAdvance<ReadVST2R, 0>;
698 def : ReadAdvance<ReadVST4R, 0>;
699 def : ReadAdvance<ReadVST8R, 0>;
706 def : ReadAdvance<ReadVExtV, 0>;
[all …]
H A DRISCVScheduleB.td56 def : ReadAdvance<ReadSHXADD, 0>;
57 def : ReadAdvance<ReadSHXADD32, 0>;
76 def : ReadAdvance<ReadRotateImm, 0>;
80 def : ReadAdvance<ReadCLZ, 0>;
81 def : ReadAdvance<ReadCLZ32, 0>;
82 def : ReadAdvance<ReadCTZ, 0>;
83 def : ReadAdvance<ReadCTZ32, 0>;
84 def : ReadAdvance<ReadCPOP, 0>;
85 def : ReadAdvance<ReadCPOP32, 0>;
86 def : ReadAdvance<ReadREV8, 0>;
[all …]
H A DRISCVSchedule.td209 def : ReadAdvance<ReadFALU16, 0>;
210 def : ReadAdvance<ReadFClass16, 0>;
211 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
212 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
219 def : ReadAdvance<ReadFDiv16, 0>;
220 def : ReadAdvance<ReadFCmp16, 0>;
221 def : ReadAdvance<ReadFMA16, 0>;
222 def : ReadAdvance<ReadFMinMax16, 0>;
223 def : ReadAdvance<ReadFMul16, 0>;
226 def : ReadAdvance<ReadFSGNJ16, 0>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td104 // These ReadAdvance entries are not used in the Falkor sched model.
105 def : ReadAdvance<ReadI, 0>;
106 def : ReadAdvance<ReadISReg, 0>;
107 def : ReadAdvance<ReadIEReg, 0>;
108 def : ReadAdvance<ReadIM, 0>;
109 def : ReadAdvance<ReadIMA, 0>;
110 def : ReadAdvance<ReadID, 0>;
111 def : ReadAdvance<ReadExtrHi, 0>;
112 def : ReadAdvance<ReadAdrBase, 0>;
113 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedKryo.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 0>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedThunderX.td192 def : ReadAdvance<ReadExtrHi, 1>;
193 def : ReadAdvance<ReadAdrBase, 2>;
194 def : ReadAdvance<ReadVLD, 2>;
200 // ReadAdvance applies to Extended registers as well, even though there is
202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
226 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
230 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
236 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td150 def : ReadAdvance<ReadExtrHi, 0>;
151 def : ReadAdvance<ReadAdrBase, 0>;
152 def : ReadAdvance<ReadVLD, 0>;
157 // ReadAdvance applies to Extended registers as well, even though there is
159 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
183 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
187 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
193 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedA55.td182 def : ReadAdvance<ReadVLD, 0>;
183 def : ReadAdvance<ReadExtrHi, 1>;
184 def : ReadAdvance<ReadAdrBase, 1>;
190 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
214 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
218 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
224 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedTSV110.td107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM3.td270 def : ReadAdvance<ReadI, 0>;
271 def : ReadAdvance<ReadISReg, 0>;
272 def : ReadAdvance<ReadIEReg, 0>;
273 def : ReadAdvance<ReadIM, 0>;
275 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
276 def : ReadAdvance<ReadID, 0>;
277 def : ReadAdvance<ReadExtrHi, 0>;
278 def : ReadAdvance<ReadAdrBase, 0>;
279 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedCyclone.td186 def : ReadAdvance<ReadExtrHi, 1>;
635 def : ReadAdvance<ReadVLD, 5>;
865 def : ReadAdvance<ReadI, 0>;
866 def : ReadAdvance<ReadISReg, 0>;
867 def : ReadAdvance<ReadIEReg, 0>;
868 def : ReadAdvance<ReadIM, 0>;
869 def : ReadAdvance<ReadIMA, 0>;
870 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedA57.td112 def : ReadAdvance<ReadI, 0>;
113 def : ReadAdvance<ReadISReg, 0>;
114 def : ReadAdvance<ReadIEReg, 0>;
115 def : ReadAdvance<ReadIM, 0>;
116 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
117 def : ReadAdvance<ReadID, 0>;
118 def : ReadAdvance<ReadExtrHi, 0>;
119 def : ReadAdvance<ReadAdrBase, 0>;
120 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM5.td609 def : ReadAdvance<ReadI, 0>;
610 def : ReadAdvance<ReadISReg, 0>;
611 def : ReadAdvance<ReadIEReg, 0>;
612 def : ReadAdvance<ReadIM, 0>;
614 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
615 def : ReadAdvance<ReadID, 0>;
616 def : ReadAdvance<ReadExtrHi, 0>;
617 def : ReadAdvance<ReadAdrBase, 0>;
618 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM4.td574 def : ReadAdvance<ReadI, 0>;
575 def : ReadAdvance<ReadISReg, 0>;
576 def : ReadAdvance<ReadIEReg, 0>;
577 def : ReadAdvance<ReadIM, 0>;
579 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
580 def : ReadAdvance<ReadID, 0>;
581 def : ReadAdvance<ReadExtrHi, 0>;
582 def : ReadAdvance<ReadAdrBase, 0>;
583 def : ReadAdvance<ReadVLD, 0>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp511 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
512 if (ReadAdvance < 0) { in collectWrites()
514 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
527 if (ReadAdvance < 0) { in collectWrites()
529 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
569 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRAWHazards() local
580 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
630 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
631 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
638 unsigned ReadAdvance = static_cast<unsigned>( in addRegisterRead() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
175 def : ReadAdvance<ReadALUsr, 0>;
176 def : ReadAdvance<ReadMUL, 0>;
177 def : ReadAdvance<ReadMAC, 1>;
178 def : ReadAdvance<ReadALU, 0>;
179 def : ReadAdvance<ReadFPMUL, 0>;
180 def : ReadAdvance<ReadFPMAC, 3>;
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
89 def : ReadAdvance<ReadMUL, 0>;
90 def : ReadAdvance<ReadMAC, 0>;
127 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
134 def : ReadAdvance<R52Read_ISS, 0>;
135 def : ReadAdvance<R52Read_EX1, 1>;
136 def : ReadAdvance<R52Read_EX2, 2>;
137 def : ReadAdvance<R52Read_F0, 0>;
138 def : ReadAdvance<R52Read_F1, 1>;
[all …]
H A DARMScheduleA57.td266 def : ReadAdvance<ReadMUL, 0>;
763 def : ReadAdvance<ReadFPMUL, 0>;
776 // def : ReadAdvance<A57ReadVFMA, 5, [A57WriteVFMA]>;
777 // def : ReadAdvance<A57ReadVFMA, 4, [A57WriteVMUL]>;
1034 // (4 or 3 ReadAdvance)
1047 // (4 or 3 ReadAdvance)
1060 // (4 or 3 ReadAdvance)
1073 // (3 or 2 ReadAdvance)
1098 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
1104 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td50 def : ReadAdvance<ReadAfterLd, 3>;
51 def : ReadAdvance<ReadAfterVecLd, 3>;
52 def : ReadAdvance<ReadAfterVecXLd, 3>;
53 def : ReadAdvance<ReadAfterVecYLd, 3>;
55 def : ReadAdvance<ReadInt2Fpu, 0>;
H A DX86ScheduleAtom.td45 def : ReadAdvance<ReadAfterLd, 3>;
46 def : ReadAdvance<ReadAfterVecLd, 3>;
47 def : ReadAdvance<ReadAfterVecXLd, 3>;
48 def : ReadAdvance<ReadAfterVecYLd, 3>;
50 def : ReadAdvance<ReadInt2Fpu, 0>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td163 def : ReadAdvance<MIVGPRRead, -2>;
171 def : ReadAdvance<MIMFMARead, -4>;

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