Searched refs:RdLo (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 4266 bits<4> RdLo;
4271 let Inst{15-12} = RdLo;
4278 bits<4> RdLo;
4283 let Inst{15-12} = RdLo;
4352 [(set GPR:$RdLo, GPR:$RdHi,
4404 bits<4> RdLo;
4409 let Inst{15-12} = RdLo;
4415 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4575 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4631 bits<4> RdLo;
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| H A D | ARMInstrThumb2.td | 687 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
688 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
690 bits<4> RdLo;
698 let Inst{15-12} = RdLo;
704 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
706 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
709 bits<4> RdLo;
717 let Inst{15-12} = RdLo;
2998 [(set rGPR:$RdLo, rGPR:$RdHi,
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| H A D | ARMInstrFormats.td | 1011 bits<4> RdLo;
1014 let Inst{15-12} = RdLo;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrAtomics.td | 431 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
433 class cmp_swap_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32common:$scratch),
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 8289 unsigned RdLo = Inst.getOperand(1).getReg(); in validateInstruction() local
8290 if(RdHi == RdLo) { in validateInstruction()
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