| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 159 unsigned Ra) { in addIntraChainConstraint() argument 160 if (Rd == Ra) in addIntraChainConstraint() 169 << Register::isPhysicalRegister(Ra) << '\n'); in addIntraChainConstraint() 187 const LiveInterval &la = LIs.getInterval(Ra); in addIntraChainConstraint() 243 unsigned Ra) { in addInterChainConstraint() argument 247 if (Chains.count(Ra)) { in addInterChainConstraint() 248 if (Rd != Ra) { in addInterChainConstraint() 251 Chains.remove(Ra); in addInterChainConstraint() 363 Register Ra = MI.getOperand(3).getReg(); in apply() local 365 if (addIntraChainConstraint(G, Rd, Ra)) in apply() [all …]
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| H A D | AArch64PBQPRegAlloc.h | 32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra); 35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
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| H A D | AArch64InstrInfo.td | 1686 GPR64:$Ra)), 3942 def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)), 3943 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3946 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3949 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 3955 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; 3958 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 3961 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 4981 V64:$Ra, 4989 V64:$Ra, [all …]
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| H A D | AArch64InstrFormats.td | 2181 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra), 2182 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> { 2186 bits<5> Ra; 2191 let Inst{14-10} = Ra; 2199 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>, 2214 [(set GPR64:$Rd, (AccNode GPR64:$Ra, 2235 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 5056 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra), 5057 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>, 5062 bits<5> Ra; [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCCodeEmitter.cpp | 114 MCRegister Ra; in expandFunctionCall() local 117 Ra = RISCV::X6; in expandFunctionCall() 120 Ra = MI.getOperand(0).getReg(); in expandFunctionCall() 123 Ra = RISCV::X1; in expandFunctionCall() 126 Ra = MI.getOperand(0).getReg(); in expandFunctionCall() 136 .addReg(Ra) in expandFunctionCall() 144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall() 147 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
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| /freebsd-13.1/crypto/openssl/crypto/ec/asm/ |
| H A D | ecp_nistz256-x86_64.pl | 2619 pxor $Ra, $Ra 2646 por $T0a, $Ra 2739 pxor $Ra, $Ra 2831 vpxor $Ra, $Ra, $Ra 2866 vpxor $T0a, $Ra, $Ra 2869 vpxor $T1a, $Ra, $Ra 2939 vpxor $Ra, $Ra, $Ra 2978 vpxor $T0a, $Ra, $Ra 2980 vpxor $T1a, $Ra, $Ra 2982 vpxor $T2a, $Ra, $Ra [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 4031 "\t$Rd, $Rn, $Rm, $Ra", 4037 bits<4> Ra; 4041 let Inst{15-12} = Ra; 4318 bits<4> Ra; 4319 let Inst{15-12} = Ra; 4339 bits<4> Ra; 4341 let Inst{15-12} = Ra; 4522 [(set GPRnopc:$Rd, (add GPR:$Ra, 4546 [(set GPRnopc:$Rd, (add GPR:$Ra, 4623 bits<4> Ra; [all …]
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| H A D | ARMInstrThumb2.td | 677 bits<4> Ra; 680 let Inst{15-12} = Ra; 2606 "usada8", "\t$Rd, $Rn, $Rm, $Ra", 2972 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2978 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 3023 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 3035 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 3102 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 3191 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), 3192 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", [all …]
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| H A D | ARMInstrFormats.td | 970 // MSW multiple w/ Ra operand 974 bits<4> Ra; 975 let Inst{15-12} = Ra; 1000 // AMulxyI with Ra operand 1004 bits<4> Ra; 1005 let Inst{15-12} = Ra;
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| /freebsd-13.1/tools/regression/iscsi/ |
| H A D | iscsi-test.sh | 153 check iscsictl -Ra 765 check iscsictl -Ra
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| /freebsd-13.1/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | Builtins.def | 1021 LIBBUILTIN(vscanf, "icC*Ra", "fS:0:", "stdio.h", ALL_LANGUAGES) 1022 LIBBUILTIN(vfscanf, "iP*RcC*Ra", "fS:1:", "stdio.h", ALL_LANGUAGES) 1023 LIBBUILTIN(vsscanf, "icC*RcC*Ra", "fS:1:", "stdio.h", ALL_LANGUAGES)
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| /freebsd-13.1/contrib/tzdata/ |
| H A D | southamerica | 1672 # From Carlos Raúl Perasso via Jesper Nørgaard Welen (2006-10-13) 1676 # From Carlos Raúl Perasso (2010-02-18): 1694 # From Carlos Raúl Perasso (2013-03-15): 1697 # From Carlos Raúl Perasso (2014-02-28):
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| H A D | NEWS | 2861 (Thanks to Carlos Raúl Perasso.) 3586 Paraguay's 2014 DST will be as predicted. (Thanks to Carlos Raúl Perasso.) 4071 (Thanks to Carlos Raúl Perasso.)
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| H A D | northamerica | 2540 # From Carlos Raúl Perasso (2015-02-02):
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 888 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 889 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 890 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 891 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2497 unsigned Ra = fieldFromInstruction(Insn, 12, 4); in DecodeSMLAInstruction() local 2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) in DecodeSMLAInstruction()
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| /freebsd-13.1/contrib/sendmail/ |
| H A D | PGPKEYS | 111 V9xOCqCWvcJ8gC+Ra+h5PN+ESy4Qqo771fNThV4C5QMQ6t8I+JPiepI+H4U19zxb
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