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Searched refs:RSP (Results 1 – 24 of 24) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp183 RegSlotPair RSP(Reg, FI); in recordReload() local
184 auto Res = Reloads[MBB].insert(RSP); in recordReload()
191 RegSlotPair RSP(Reg, FI); in hasReload() local
192 return Reloads.count(MBB) && Reloads[MBB].count(RSP); in hasReload()
245 for (auto &RSP : GlobalIndices[EHPad]) in reset() local
246 ReservedSlots.insert(RSP.second); in reset()
256 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() argument
/freebsd-13.1/sys/amd64/amd64/
H A Dbpf_jit_machdep.c207 MOVrq(RSP, RBP); in bpf_jit_compile()
208 SUBib(BPF_MEMWORDS * sizeof(uint32_t), RSP); in bpf_jit_compile()
401 MOVobd(RSP, RSI, EAX); in bpf_jit_compile()
406 MOVobd(RSP, RSI, EDX); in bpf_jit_compile()
416 MOVomd(EAX, RSP, RSI); in bpf_jit_compile()
421 MOVomd(EDX, RSP, RSI); in bpf_jit_compile()
H A Dbpf_jit_machdep.h46 #define RSP 4 macro
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp161 {codeview::RegisterId::RSP, X86::RSP}, in initLLVMToSEHAndCVRegMapping()
352 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
625 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
653 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
690 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
726 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
762 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
763 return X86::RSP; in getX86SubSuperRegisterOrZero()
H A DX86MCCodeEmitter.cpp601 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrControl.td328 // RSP is marked as a use to prevent stack-pointer assignments that appear
331 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
364 isCodeGenOnly = 1, Uses = [RSP, SSP] in {
398 Uses = [RSP, SSP],
419 Uses = [RSP, SSP],
438 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86LoadValueInjectionRetHardening.cpp99 X86::RSP, false, 0) in runOnMachineFunction()
H A DX86RegisterInfo.td176 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
437 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
463 R8, R9, R11, RIP, RSP)>;
466 RIP, RSP)>;
484 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
489 // GR64_NOSP - GR64 registers except RSP (and RIP).
490 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
497 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
H A DX86FrameLowering.cpp865 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP); in emitStackProbeInlineWindowsCoreCLR64()
935 X86::RSP, false, RCXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
939 X86::RSP, false, RDXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
946 .addReg(X86::RSP) in emitStackProbeInlineWindowsCoreCLR64()
1011 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP; in emitStackProbeCall()
1519 .addUse(X86::RSP) in emitPrologue()
1525 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri8), X86::RSP) in emitPrologue()
1526 .addUse(X86::RSP) in emitPrologue()
2067 TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true); in emitEpilogue()
2835 ScratchReg = IsLP64 ? X86::RSP : X86::ESP; in adjustForSegmentedStacks()
[all …]
H A DX86RegisterInfo.cpp66 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
543 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs()
844 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
H A DX86IndirectThunks.cpp245 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk()
H A DX86SpeculativeLoadHardening.cpp1544 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP) in mergePredStateIntoSP()
1545 .addReg(X86::RSP) in mergePredStateIntoSP()
1562 .addReg(X86::RSP); in extractPredStateFromSP()
1591 } else if (BaseMO.getReg() == X86::RSP) { in hardenLoadAddr()
2152 .addReg(/*Base*/ X86::RSP) in tracePredStateThroughCall()
H A DX86InstrCompiler.td52 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
117 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
134 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
161 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
466 // All calls clobber the non-callee saved registers. RSP is marked as
475 usesCustomInserter = 1, Uses = [RSP, SSP] in {
512 Uses = [RSP, SSP],
H A DX86InstrInfo.td349 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
1299 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1376 let Uses = [RSP] in
1389 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
1409 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1437 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1447 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1450 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
H A DX86FixupLEAs.cpp580 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
H A DX86CallingConv.td426 // Return: could return in any GP register save RSP and R12.
596 // Use all/any GP registers for args, except RSP.
H A DX86InstrInfo.cpp9071 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) || in getOutliningType()
9072 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) || in getOutliningType()
9073 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) in getOutliningType()
H A DX86ISelDAGToDAG.cpp393 (RegNode->getReg() == X86::RSP)) in shouldAvoidImmediateInstFormsForSize()
H A DX86ISelLowering.cpp26856 .Case("rsp", X86::RSP) in getRegisterByName()
29333 DAG.getRegister(X86::RSP, MVT::i64), // Base in emitLockedStackOp()
33003 Register physSPReg = TFI.Uses64BitFramePtr ? X86::RSP : X86::ESP; in EmitLoweredProbedAlloca()
33120 IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca()
/freebsd-13.1/contrib/llvm-project/llvm/lib/DebugInfo/CodeView/
H A DSymbolRecordMapping.cpp511 case EncodedFramePtrReg::StackPtr: return RegisterId::RSP; in decodeFramePtrReg()
546 case RegisterId::RSP: in encodeFramePtrReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h192 ENTRY(RSP) \
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def227 CV_REGISTER(RSP, 335)
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1304 IndexReg == X86::ESP || IndexReg == X86::RSP) { in CheckBaseRegAndIndexRegAndScale()
2558 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in ParseIntelOperand()
2559 (IndexReg == X86::ESP || IndexReg == X86::RSP)) in ParseIntelOperand()
3928 is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP); in applyLVICFIMitigation()
/freebsd-13.1/contrib/wpa/wpa_supplicant/
H A DChangeLog393 CTRL-REQ/RSP-PSK_PASSPHRASE)
762 and EAP-AKA' (CTRL-REQ-SIM and CTRL-RSP-SIM commands over control