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Searched refs:ROR (Results 1 – 25 of 33) sorted by relevance

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/freebsd-13.1/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl84 $ROR="rotrdi";
96 $ROR="rotrwi";
134 $ROR $a0,$e,$Sigma1[0]
135 $ROR $a1,$e,$Sigma1[1]
140 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
147 $ROR $a0,$a,$Sigma0[0]
148 $ROR $a1,$a,$Sigma0[1]
173 $ROR $a0,@X[($i+1)%16],$sigma0[0]
174 $ROR $a1,@X[($i+1)%16],$sigma0[1]
175 $ROR $t0,@X[($i+14)%16],$sigma1[0]
[all …]
/freebsd-13.1/sys/crypto/openssl/arm/
H A Dsha1-armv4-large.S51 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
57 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
76 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
82 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
101 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
107 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
126 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
132 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
151 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
157 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td16 /// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
92 defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h37 ROR, enumerator
58 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
79 case 3: return AArch64_AM::ROR; in getShiftType()
107 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td143 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedPredicates.td51 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
H A DAArch64ISelDAGToDAG.cpp503 return AArch64_AM::ROR; in getShiftTypeForNode()
565 if (!AllowROR && ShType == AArch64_AM::ROR) in SelectShiftedRegister()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h47 ROR, ///< Bit rotate right. enumerator
H A DAVRISelLowering.cpp249 NODE(ROR); in getTargetNodeName()
324 Opc8 = AVRISD::ROR; in LowerShifts()
/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h181 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, in ROR() function
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h498 ROR, enumerator
/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1757 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRtPCRelative()
6362 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRImmediateARM()
6501 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRegister()
8351 rotated = ROR(R[m], rotation); in EmulateSXTB()
8406 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTB()
8436 rotated = ROR(R[m], rotation); in EmulateSXTH()
8491 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTH()
8521 rotated = ROR(R[m], rotation); in EmulateUXTB()
8576 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateUXTB()
8604 rotated = ROR(R[m], rotation); in EmulateUXTH()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td960 "ROR(8|16|32|64)m(1|i)")>;
1005 "ROR(8|16|32|64)mCL",
H A DX86ScheduleAtom.td506 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86SchedBroadwell.td1115 "ROR(8|16|32|64)m(1|i)")>;
1192 "ROR(8|16|32|64)mCL",
H A DX86SchedHaswell.td1193 "ROR(8|16|32|64)m(1|i)")>;
1323 "ROR(8|16|32|64)mCL",
H A DX86SchedSkylakeClient.td1181 "ROR(8|16|32|64)m(1|i)")>;
1264 "ROR(8|16|32|64)mCL",
H A DX86SchedSkylakeServer.td1452 "ROR(8|16|32|64)m(1|i)")>;
1623 "ROR(8|16|32|64)mCL",
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
H A DARMScheduleSwift.td154 // ASR,LSL,ROR,RRX
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoB.td297 def ROR : ALU_rr<0b0110000, 0b101, "ror">,
799 def : PatGprGpr<rotr, ROR>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1339 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1445 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
3205 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
3227 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td274 defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">;
/freebsd-13.1/sys/dev/axgbe/
H A Dxgbe-dev.c2454 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2577 case Mips::ROR: in tryExpandInstruction()
4881 if (Inst.getOpcode() == Mips::ROR) { in expandRotation()
4897 case Mips::ROR: in expandRotation()

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