| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 521 unsigned LHSMask, unsigned RHSMask, InstCombiner::BuilderTy &Builder) { in foldLogOpOfMaskedICmpsAsymmetric() argument
531 RHSMask = conjugateICmpMask(RHSMask); in foldLogOpOfMaskedICmpsAsymmetric()
533 if ((LHSMask & Mask_NotAllZeros) && (RHSMask & BMask_Mixed)) { in foldLogOpOfMaskedICmpsAsymmetric()
539 } else if ((LHSMask & BMask_Mixed) && (RHSMask & Mask_NotAllZeros)) { in foldLogOpOfMaskedICmpsAsymmetric()
562 unsigned RHSMask = MaskPair->second; in foldLogOpOfMaskedICmps() local
563 unsigned Mask = LHSMask & RHSMask; in foldLogOpOfMaskedICmps()
568 LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask, in foldLogOpOfMaskedICmps()
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| H A D | InstCombineVectorOps.cpp | 2652 ArrayRef<int> RHSMask; in visitShuffleVectorInst() local
2656 RHSMask = RHSShuffle->getShuffleMask(); in visitShuffleVectorInst()
2692 eltMask = RHSMask[Mask[i]-LHSWidth]; in visitShuffleVectorInst()
2725 if (isSplat || newMask == LHSMask || newMask == RHSMask || newMask == Mask) { in visitShuffleVectorInst()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 9196 uint32_t RHSMask = getPermuteMask(DAG, RHS); in performAndCombine() local
9197 if (LHSMask != ~0u && RHSMask != ~0u) { in performAndCombine()
9200 if (LHSMask > RHSMask) { in performAndCombine()
9201 std::swap(LHSMask, RHSMask); in performAndCombine()
9220 uint32_t Mask = LHSMask & RHSMask; in performAndCombine()
9293 uint32_t RHSMask = getPermuteMask(DAG, RHS); in performOrCombine() local
9294 if (LHSMask != ~0u && RHSMask != ~0u) { in performOrCombine()
9297 if (LHSMask > RHSMask) { in performOrCombine()
9298 std::swap(LHSMask, RHSMask); in performOrCombine()
9314 RHSMask &= ~LHSUsedLanes; in performOrCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5927 APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5); in PerformDAGCombine() local
5929 SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) { in PerformDAGCombine()
6001 APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5); in PerformDAGCombine() local
6003 SimplifyDemandedBits(RHS, RHSMask, DCI)) { in PerformDAGCombine()
6032 APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 4); in PerformDAGCombine() local
6034 SimplifyDemandedBits(RHS, RHSMask, DCI)) { in PerformDAGCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6332 const APInt &RHSMask = N1O1C->getAPIntValue(); in visitORLike() local
6334 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && in visitORLike()
6335 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { in visitORLike()
6339 DAG.getConstant(LHSMask | RHSMask, DL, VT)); in visitORLike()
6956 SDValue RHSMask; // AND value if any. in MatchRotate() local
6957 matchRotateHalf(DAG, RHS, RHSShift, RHSMask); in MatchRotate()
6974 extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL)) in MatchRotate()
6999 std::swap(LHSMask, RHSMask); in MatchRotate()
7027 if (LHSMask.getNode() || RHSMask.getNode()) { in MatchRotate()
7036 if (RHSMask.getNode()) { in MatchRotate()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 15887 int RHSMask[4] = {-1, -1, -1, -1}; in lowerShuffleAsLanePermuteAndSHUFP() local
15897 auto &LaneMask = (i & 1) ? RHSMask : LHSMask; in lowerShuffleAsLanePermuteAndSHUFP()
15903 SDValue RHS = DAG.getVectorShuffle(VT, DL, V1, V2, RHSMask); in lowerShuffleAsLanePermuteAndSHUFP()
41795 SmallVector<int, 64> LHSMask, RHSMask, CondMask; in combineSelect() local
41798 getTargetShuffleMask(RHS.getNode(), SimpleVT, true, RHSOps, RHSMask)) { in combineSelect()
41802 RHSMask[i] = 0x80; in combineSelect()
41809 getConstVector(RHSMask, SimpleVT, DAG, DL, true)); in combineSelect()
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