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Searched refs:READ_REG32 (Results 1 – 13 of 13) sorted by relevance

/freebsd-13.1/sys/dev/qlxgbe/
H A Dql_isr.c791 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); in ql_mbx_isr()
797 data = READ_REG32(ha, Q8_FW_MBOX0); in ql_mbx_isr()
807 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); in ql_mbx_isr()
809 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); in ql_mbx_isr()
815 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); in ql_mbx_isr()
837 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16)); in ql_mbx_isr()
852 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); in ql_mbx_isr()
853 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); in ql_mbx_isr()
895 ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); in ql_mbx_isr()
896 ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); in ql_mbx_isr()
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H A Dql_inline.h57 if ((READ_REG32(ha, sem_reg) & BIT_0)) in qla_sem_lock()
79 READ_REG32(ha, sem_reg); in qla_sem_unlock()
93 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0); in qla_get_optics()
H A Dql_misc.c75 if (READ_REG32(ha, wnd_reg) == addr) in ql_rdwr_indreg32()
87 *val = READ_REG32(ha, Q8_WILD_CARD); in ql_rdwr_indreg32()
678 mem_off = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR)); in qla_load_fw_from_flash()
679 mem_size = READ_REG32(ha, Q8_BOOTLD_SIZE); in qla_load_fw_from_flash()
730 data = READ_REG32(ha, Q8_CMDPEG_STATE); in qla_init_from_flash()
764 val = READ_REG32(ha, Q8_CMDPEG_STATE); in ql_init_hw()
779 val = READ_REG32(ha, Q8_CMDPEG_STATE); in ql_init_hw()
786 ha->fw_ver_major = READ_REG32(ha, Q8_FW_VER_MAJOR); in ql_init_hw()
787 ha->fw_ver_minor = READ_REG32(ha, Q8_FW_VER_MINOR); in ql_init_hw()
788 ha->fw_ver_sub = READ_REG32(ha, Q8_FW_VER_SUB); in ql_init_hw()
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H A Dql_hw.c1414 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL); in qla_mbx_cmd()
1449 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); in qla_mbx_cmd()
1452 data = READ_REG32(ha, Q8_FW_MBOX0); in qla_mbx_cmd()
1479 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2))); in qla_mbx_cmd()
2881 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX); in qla_confirm_9kb_enable()
3812 link_state = READ_REG32(ha, Q8_LINK_STATE); in ql_update_link_state()
3845 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE); in ql_hw_check_health()
3860 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT); in ql_hw_check_health()
3880 peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1); in ql_hw_check_health()
3881 peg_halt_status2 = READ_REG32(ha, Q8_PEG_HALT_STATUS2); in ql_hw_check_health()
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H A Dql_ioctl.c118 u.rv->val = READ_REG32(ha, u.rv->reg); in ql_eioctl()
H A Dql_hw.h205 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
/freebsd-13.1/sys/dev/qlxgb/
H A Dqla_inline.h65 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT)) in qla_sem_lock()
87 READ_REG32(ha, sem_reg); in qla_sem_unlock()
101 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0); in qla_get_optics()
141 mac_lo = READ_REG32(ha, mac_crb_addr); in qla_read_mac_addr()
142 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4)); in qla_read_mac_addr()
H A Dqla_reg.h230 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
231 #define READ_OFFSET32(ha, off) READ_REG32(ha, off)
H A Dqla_hw.c442 data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP); in qla_issue_cmd()
451 cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP); in qla_issue_cmd()
452 cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1); in qla_issue_cmd()
453 cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2); in qla_issue_cmd()
454 cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3); in qla_issue_cmd()
1722 hw->txr_comp, hw->txr_free, hw->txr_next, READ_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000)))); in qla_hw_tx_done_locked()
1758 link_state = READ_REG32(ha, Q8_LINK_STATE); in qla_update_link_state()
/freebsd-13.1/sys/dev/qlxge/
H A Dqls_dump.c382 data = READ_REG32(ha, reg); in qls_wait_reg_rdy()
621 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); in qls_rd_serdes_reg()
811 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); in qls_unpause_mpi_risc()
854 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); in qls_get_intr_states()
875 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); in qls_rd_xgmac_reg()
1224 lo_val = READ_REG32(ha,\ in qls_get_probe()
1236 hi_val = READ_REG32(ha,\ in qls_get_probe()
1536 READ_REG32(ha, \ in qls_get_mac_proto_regs()
1539 result_data = READ_REG32(ha,\ in qls_get_mac_proto_regs()
1623 READ_REG32(ha, i * sizeof(uint32_t)); in qls_mpi_core_dump()
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H A Dqls_hw.c903 ha->rev_id = READ_REG32(ha, Q81_CTL_REV_ID); in qls_init_hw_if()
961 data32 = READ_REG32(ha, Q81_CTL_CONFIG); in qls_wait_for_config_reg_bits()
1311 link_state = READ_REG32(ha, Q81_CTL_STATUS); in qls_update_link_state()
1761 data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR); in qls_wait_for_flash_ready()
1799 *data = READ_REG32(ha, Q81_CTL_FLASH_DATA); in qls_rd_flash32()
1890 data = READ_REG32(ha, Q81_CTL_SEMAPHORE); in qls_sem_lock()
1915 data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR); in qls_wait_for_proc_addr_ready()
1954 *data = READ_REG32(ha, Q81_CTL_PROC_DATA); in qls_proc_addr_rd_reg()
1999 data = READ_REG32(ha, Q81_CTL_RESET); in qls_hw_nic_reset()
2040 data = READ_REG32(ha, Q81_CTL_STATUS); in qls_hw_reset()
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H A Dqls_isr.c367 status = READ_REG32(ha, Q81_CTL_STATUS); in qls_isr()
378 status = READ_REG32(ha, Q81_CTL_INTR_STATUS1); in qls_isr()
H A Dqls_hw.h900 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro