Searched refs:RBGPR (Results 1 – 3 of 3) sorted by relevance
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo() local143 (void)RBGPR; in ARMRegisterBankInfo()147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()161 assert(RBGPR.covers(*TRI.getRegClass( in ARMRegisterBankInfo()[all …]
32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo() local33 (void)RBGPR; in X86RegisterBankInfo()34 assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization."); in X86RegisterBankInfo()38 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()40 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); in X86RegisterBankInfo()
53 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() local54 (void)RBGPR; in AArch64RegisterBankInfo()55 assert(&AArch64::GPRRegBank == &RBGPR && in AArch64RegisterBankInfo()70 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()72 assert(RBGPR.getSize() == 128 && "GPRs should hold up to 128-bit"); in AArch64RegisterBankInfo()105 CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); in AArch64RegisterBankInfo()106 CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); in AArch64RegisterBankInfo()107 CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR); in AArch64RegisterBankInfo()