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Searched refs:PtrReg (Results 1 – 9 of 9) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp416 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
417 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
436 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
547 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
548 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
550 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1166 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1177 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1181 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1185 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1192 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0); in applyMappingLoad()
1193 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8); in applyMappingLoad()
3297 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3305 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3316 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
3317 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
[all …]
H A DAMDGPULegalizerInfo.cpp2472 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2473 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2478 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
2523 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2531 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2539 B.buildLoadFromOffset(WideLoad, PtrReg, *MMO, 0); in legalizeLoad()
2575 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
2579 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
2589 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp2412 Register PtrReg = MI.getOperand(1).getReg(); in selectG_AMDGPU_ATOMIC_CMPXCHG() local
2413 const LLT PtrTy = MRI->getType(PtrReg); in selectG_AMDGPU_ATOMIC_CMPXCHG()
3427 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm() local
3429 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm()
3443 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
3450 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3477 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdSgpr() local
3482 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdSgpr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2368 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2376 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2378 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2381 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2386 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2393 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2398 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
2401 LHS = PtrReg.first; in applyCombineAddP2IToPtrAdd()
H A DLegalizerHelper.cpp959 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
966 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
2884 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
2921 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
2961 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
2965 PtrReg, *LargeMMO); in lowerLoad()
2996 Register PtrReg = StoreMI.getPointerReg(); in lowerStore() local
3024 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); in lowerStore()
3045 LLT PtrTy = MRI.getType(PtrReg); in lowerStore()
3050 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); in lowerStore()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11260 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
11322 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11327 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11348 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11392 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12266 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
12336 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12341 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12373 .addReg(PtrReg); in EmitInstrWithCustomInserter()
12397 .addReg(PtrReg); in EmitInstrWithCustomInserter()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2740 const Register PtrReg = I.getOperand(1).getReg(); in select() local
2741 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2745 assert(MRI.getType(PtrReg).isPointer() && in select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4680 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4681 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()