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Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance

/freebsd-13.1/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c592 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
594 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
608 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
613 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
616 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
620 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra124_car.h56 #define PLLE_SS_CNTL 0x068 macro
/freebsd-13.1/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c785 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
787 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
799 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
808 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
811 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
815 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra210_car.h60 #define PLLE_SS_CNTL 0x068 macro