| /freebsd-13.1/share/misc/ |
| H A D | pci_vendors | 41 7a09 PCI-to-PCI Bridge
49 7a19 PCI-to-PCI Bridge
51 7a29 PCI-to-PCI Bridge
3747 7915 RS690 PCI to PCI Bridge (PCI Express Port 1)
3748 7916 RS690 PCI to PCI Bridge (PCI Express Port 2)
3749 7917 RS690 PCI to PCI Bridge (PCI Express Port 3)
3762 7935 RS600 PCI to PCI Bridge (PCI Express Port 1)
3763 7936 RS600 PCI to PCI Bridge (PCI Express Port 2)
5853 0125 uPD720400 PCI Express - PCI/PCI-X Bridge
8680 8114 PEX 8114 PCI Express-to-PCI/PCI-X Bridge
[all …]
|
| /freebsd-13.1/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | mpc8641_hpcn_36b.dts | 134 /* IDSEL 0x11 func 0 - PCI slot 1 */
140 /* IDSEL 0x11 func 1 - PCI slot 1 */
146 /* IDSEL 0x11 func 2 - PCI slot 1 */
152 /* IDSEL 0x11 func 3 - PCI slot 1 */
158 /* IDSEL 0x11 func 4 - PCI slot 1 */
164 /* IDSEL 0x11 func 5 - PCI slot 1 */
170 /* IDSEL 0x11 func 6 - PCI slot 1 */
176 /* IDSEL 0x11 func 7 - PCI slot 1 */
182 /* IDSEL 0x12 func 0 - PCI slot 2 */
188 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
|
| H A D | mpc8641_hpcn.dts | 167 /* IDSEL 0x11 func 0 - PCI slot 1 */
173 /* IDSEL 0x11 func 1 - PCI slot 1 */
179 /* IDSEL 0x11 func 2 - PCI slot 1 */
185 /* IDSEL 0x11 func 3 - PCI slot 1 */
191 /* IDSEL 0x11 func 4 - PCI slot 1 */
197 /* IDSEL 0x11 func 5 - PCI slot 1 */
203 /* IDSEL 0x11 func 6 - PCI slot 1 */
209 /* IDSEL 0x11 func 7 - PCI slot 1 */
215 /* IDSEL 0x12 func 0 - PCI slot 2 */
221 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
|
| H A D | mpc8572ds.dtsi | 249 /* IDSEL 0x11 func 0 - PCI slot 1 */
255 /* IDSEL 0x11 func 1 - PCI slot 1 */
261 /* IDSEL 0x11 func 2 - PCI slot 1 */
267 /* IDSEL 0x11 func 3 - PCI slot 1 */
273 /* IDSEL 0x11 func 4 - PCI slot 1 */
279 /* IDSEL 0x11 func 5 - PCI slot 1 */
285 /* IDSEL 0x11 func 6 - PCI slot 1 */
291 /* IDSEL 0x11 func 7 - PCI slot 1 */
297 /* IDSEL 0x12 func 0 - PCI slot 2 */
303 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
|
| H A D | p2020ds.dtsi | 219 // IDSEL 0x11 func 0 - PCI slot 1
223 // IDSEL 0x11 func 1 - PCI slot 1
227 // IDSEL 0x11 func 2 - PCI slot 1
231 // IDSEL 0x11 func 3 - PCI slot 1
235 // IDSEL 0x11 func 4 - PCI slot 1
239 // IDSEL 0x11 func 5 - PCI slot 1
243 // IDSEL 0x11 func 6 - PCI slot 1
247 // IDSEL 0x11 func 7 - PCI slot 1
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qca,ath9k.txt | 4 node is expected to be specified as a child node of the PCI controller to
8 - compatible: For PCI and PCIe devices this should be an identifier following
9 the format as defined in "PCI Bus Binding to Open Firmware"
11 where VVVV is the PCI vendor ID and DDDD is PCI device ID.
12 Typically QCA's PCI vendor ID 168c is used while the PCI device
41 In this example, the node is defined as child node of the PCI controller:
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/pci/ |
| H A D | ralink,rt3883-pci.txt | 1 * Mediatek/Ralink RT3883 PCI controller
29 interrupt controller and the PCI host bridge.
48 b) PCI host bridge:
63 - bus-range: PCI bus numbers covered
65 - ranges: specifies the ranges for the PCI memory and I/O regions
68 - interrupt-map: standard PCI properties to define the mapping of the
69 PCI interface to interrupt numbers.
71 The PCI host bridge node might have additional sub-nodes representing
72 the onboard PCI devices/PCI slots. Each such sub-node must have the
80 If a given sub-node represents a PCI bridge it must have following
[all …]
|
| H A D | faraday,ftpci100.txt | 1 Faraday Technology FTPCI100 PCI Host Bridge
3 This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
5 plain and dual PCI. The plain version embeds a cascading interrupt controller
9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
35 PCI clock (PCICLK). If these are not present, they are assumed to be
36 hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
38 clock and "PCICLK" for the PCI-side clock.
88 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
89 <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
90 <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
[all …]
|
| H A D | 83xx-512x-pci.txt | 1 * Freescale 83xx and 512x PCI bridges
3 Freescale 83xx and 512x SOCs include the same PCI bridge core.
7 The first is for the internal PCI bridge registers
8 The second is for the PCI config space access registers
14 /* IDSEL 0x0E -mini PCI */
20 /* IDSEL 0x0F - PCI slot */
|
| H A D | fsl,pci.txt | 1 * Bus Enumeration by Freescale PCI-X Agent
3 Typically any Freescale PCI-X bridge hardware strapped into Agent mode
5 all mezzanines to be PCI-X Agents, but one per system may still
8 The property defined below will allow a PCI-X bridge to be used for bus
17 /* PCI-X bridge known to be PrPMC Monarch */
|
| H A D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
31 PCI in either RC mode or EP mode.
63 phys: phandle to generic Keystone SerDes PHY for PCI
64 phy-names: name of the generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
69 DesignWare DT Properties not applicable for Keystone PCI
93 PCI in either RC mode or EP mode.
|
| H A D | pci.txt | 1 PCI bus bridges have standardized Device Tree bindings:
3 PCI Bus Binding to: IEEE Std 1275-1994
15 If present this property assigns a fixed PCI domain number to a host bridge,
22 If present this property specifies PCI gen for link capability. Host
36 PCI-PCI Bridge properties
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
|
| H A D | mobiveil-pcie.txt | 27 - bus-range: PCI bus numbers covered
35 interrupt-map: standard PCI properties to define the mapping of the
36 PCI interface to interrupt numbers.
37 - ranges: ranges for the PCI memory regions (I/O space region is not
39 Please refer to the standard PCI bus binding document for a more
|
| H A D | xilinx-pcie.txt | 13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
15 - ranges: ranges for the PCI memory regions (I/O space region is not
17 Please refer to the standard PCI bus binding document for a more
21 - bus-range: PCI bus numbers covered
|
| H A D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
29 PCI root complex
|
| H A D | host-generic-pci.yaml | 7 title: Generic PCI host controller
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
23 geography of a PCI bus address by concatenating the various components to
48 ThunderX PCI host controller for pass-1.x silicon
50 Firmware-initialized PCI host controller to on-chip devices found on
85 CAM or ECAM compliant PCI host controllers without any quirks
|
| H A D | xilinx-nwl-pcie.txt | 21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
22 mapping of the PCI interface to interrupt numbers.
23 - ranges: ranges for the PCI memory regions (I/O space region is not
25 Please refer to the standard PCI bus binding document for a more
|
| H A D | altera-pcie.txt | 19 standard PCI regions.
20 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
26 - bus-range: PCI bus numbers covered
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/virtio/ |
| H A D | iommu.txt | 1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
4 discovered dynamically by the PCI probing infrastructure. However the
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
42 * The IOMMU manages all functions in this PCI domain except
|
| /freebsd-13.1/sys/dev/pci/ |
| H A D | pcib_if.m | 56 # Return the number of slots on the attached PCI bus.
64 # Return the number of functions on the attached PCI bus.
71 # Read configuration space on the PCI bus. The bus, slot and func
87 # Write configuration space on the PCI bus. The bus, slot and func
180 # Return the PCI Routing Identifier (RID) for the device.
199 # Return non-zero if PCI ARI is enabled, or zero otherwise
206 # Decode a PCI Routing Identifier (RID) into PCI bus/slot/function
217 # Request control of PCI features from host firmware, if any.
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/x86/ |
| H A D | ce4100.txt | 47 The PCI node
49 This node describes the PCI bus on the SoC. Its property should be
56 to contain at least the reg property containing the PCI bus address and
57 compatible property according to "PCI Bus Binding Revision 2.1".
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-pxa-pci-ce4100.txt | 4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
|
| /freebsd-13.1/sys/contrib/device-tree/src/powerpc/ |
| H A D | amigaone.dts | 45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
47 0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
69 /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
34 is used for MSI messaging. The address of MSIIR in PCI address space is
83 Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
94 In the PAMU, each PCI controller is given only one primary window. The
96 Because PCI devices must be able to DMA to memory, the primary window must
109 this. The address specified in the msi-address-64 property is the PCI
|
| /freebsd-13.1/sys/contrib/device-tree/Bindings/net/ |
| H A D | cavium-mdio.txt | 35 Several mdio buses may be gathered as children of a single PCI
36 device, this PCI device is the nexus of the buses.
42 - reg: The PCI device and function numbers of the nexus device.
|