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Searched refs:OrigReg (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp555 Register OrigReg = U.getReg(); in colorChain() local
556 U.setReg(Substs[OrigReg]); in colorChain()
560 ToErase.push_back(OrigReg); in colorChain()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTailDuplicator.h101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTailDuplicator.cpp336 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg, in addSSAUpdateEntry() argument
339 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
345 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
346 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
H A DInlineSpiller.cpp1257 Register OrigReg = OrigLI.reg(); in isSpillCandBB() local
1258 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
H A DSplitKit.cpp343 unsigned OrigReg = VRM.getOriginal(CurLI->reg()); in isOriginalEndpoint() local
344 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp467 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
469 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
475 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
H A DLegalizerHelper.cpp1542 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { in widenWithUnmerge() argument
1544 LLT OrigTy = MRI.getType(OrigReg); in widenWithUnmerge()
1568 UnmergeResults[0] = OrigReg; in widenWithUnmerge()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp4130 const SCEV *OrigReg; member
4133 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4143 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4192 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4197 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4226 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4241 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4243 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
4256 if (F.ScaledReg == OrigReg) { in GenerateCrossUseConstantOffsets()
4285 if (BaseReg != OrigReg) in GenerateCrossUseConstantOffsets()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h165 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1663 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1674 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1676 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1678 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1688 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()