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Searched refs:OperandType (Results 1 – 25 of 79) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DAsmWriterInst.h35 } OperandType; member
54 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {} in OperandType() function
58 : OperandType(op), Str(LitStr) {} in OperandType() function
63 : OperandType(op), MIOpNo(_MIOpNo), Str(Printer), MiModifier(Modifier), in OperandType() function
67 if (OperandType != Other.OperandType || Str != Other.Str) return true;
68 if (OperandType == isMachineInstrOperand)
100 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand) in AddLiteralString()
H A DAsmWriterInst.cpp24 if (OperandType == isLiteralTextOperand) { in getCode()
30 if (OperandType == isLiteralStatementOperand) in getCode()
181 OpInfo.OperandType == "MCOI::OPERAND_PCREL"); in AsmWriterInst()
H A DWebAssemblyDisassemblerEmitter.cpp121 assert(Op.OperandType != "MCOI::OPERAND_UNKNOWN"); in emitWebAssemblyDisassemblerTables()
122 CurOperandList.push_back(Op.OperandType); in emitWebAssemblyDisassemblerTables()
H A DCodeGenInstruction.cpp79 std::string OperandType = "OPERAND_UNKNOWN"; in CGIOperandList() local
85 OperandType = std::string(Rec->getValueAsString("OperandType")); in CGIOperandList()
90 OperandType = std::string(Rec->getValueAsString("OperandType")); in CGIOperandList()
118 OperandType = "OPERAND_REGISTER"; in CGIOperandList()
138 std::string(EncoderMethod), OperandNamespace + "::" + OperandType, in CGIOperandList()
H A DCodeGenInstruction.h95 std::string OperandType; member
123 OperandType(OT), MIOperandNo(MION), MINumOperands(MINO), in OperandInfo()
H A DX86DisassemblerTables.cpp47 static inline const char* stringForOperandType(OperandType type) { in stringForOperandType()
825 typedef SmallVector<std::pair<OperandEncoding, OperandType>, in emitInstructionInfo()
835 OperandType Type = (OperandType)Operand.type; in emitInstructionInfo()
865 OperandType Type = (OperandType)Operand.type; in emitInstructionInfo()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h56 enum OperandType { enum
95 uint8_t OperandType; variable
117 return OperandType >= MCOI::OPERAND_FIRST_GENERIC && in isGenericType()
118 OperandType <= MCOI::OPERAND_LAST_GENERIC; in isGenericType()
123 return OperandType - MCOI::OPERAND_FIRST_GENERIC; in getGenericTypeIndex()
127 return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM && in isGenericImm()
128 OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM; in isGenericImm()
133 return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM; in getGenericImmIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/Disassembler/
H A DM68kDisassembler.cpp490 enum class OperandType { in getInstruction() enum
496 SmallVector<OperandType, 6> OpType(NumOperands, OperandType::Invalid); in getInstruction()
530 assert(((OpType[MIOpIdx] == OperandType::Invalid) || in getInstruction()
531 (OpType[MIOpIdx] == OperandType::Reg)) && in getInstruction()
533 OpType[MIOpIdx] = OperandType::Reg; in getInstruction()
543 assert(((OpType[MIOpIdx] == OperandType::Invalid) || in getInstruction()
544 (OpType[MIOpIdx] == OperandType::Imm)) && in getInstruction()
546 OpType[MIOpIdx] = OperandType::Imm; in getInstruction()
585 case OperandType::Invalid: in getInstruction()
588 case OperandType::Imm: in getInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.td146 let OperandType = "OPERAND_LOCAL" in
149 let OperandType = "OPERAND_GLOBAL" in {
158 let OperandType = "OPERAND_I32IMM" in
161 let OperandType = "OPERAND_I64IMM" in
164 let OperandType = "OPERAND_F32IMM" in
167 let OperandType = "OPERAND_F64IMM" in
185 let OperandType = "OPERAND_TABLE" in
188 let OperandType = "OPERAND_OFFSET32" in
191 let OperandType = "OPERAND_OFFSET64" in
199 let OperandType = "OPERAND_TAG" in
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H A DWebAssemblyMCInstLower.cpp218 if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) { in lower()
242 } else if (Info.OperandType == WebAssembly::OPERAND_SIGNATURE) { in lower()
252 } else if (Info.OperandType == WebAssembly::OPERAND_HEAPTYPE) { in lower()
H A DWebAssemblySetP2AlignOperands.cpp65 assert(MI.getDesc().OpInfo[OperandNo].OperandType == in rewriteP2Align()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h118 enum OperandType { enum
122 inline bool isVpred(OperandType op) { in isVpred()
126 return isVpred(static_cast<OperandType>(op)); in isVpred()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp97 << int(Info.OperandType) << "\n"); in encodeInstruction()
98 switch (Info.OperandType) { in encodeInstruction()
143 switch (Info.OperandType) { in encodeInstruction()
/freebsd-13.1/contrib/llvm-project/clang/include/clang/Sema/
H A DDelayedDiagnostic.h163 DD.ForbiddenTypeData.OperandType = type.getAsOpaquePtr(); in makeForbiddenType()
218 return QualType::getFromOpaquePtr(ForbiddenTypeData.OperandType); in getForbiddenTypeOperand()
250 void *OperandType; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsBaseInfo.h132 enum OperandType : unsigned { enum
/freebsd-13.1/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp395 const char *CFIProgram::operandTypeString(CFIProgram::OperandType OT) { in operandTypeString()
421 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx]; in getOperandAsUnsigned()
466 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx]; in getOperandAsSigned()
792 ArrayRef<CFIProgram::OperandType[CFIProgram::MaxOperands]>
794 static OperandType OpTypes[DW_CFA_restore + 1][MaxOperands]; in getOperandTypes()
797 return ArrayRef<OperandType[MaxOperands]>(&OpTypes[0], DW_CFA_restore + 1); in getOperandTypes()
850 return ArrayRef<OperandType[MaxOperands]>(&OpTypes[0], DW_CFA_restore + 1); in getOperandTypes()
860 OperandType Type = getOperandTypes()[Opcode][OperandIdx]; in printOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td878 let OperandType = opType#"_INT16";
884 let OperandType = opType#"_FP16";
890 let OperandType = opType#"_INT32";
896 let OperandType = opType#"_FP32";
902 let OperandType = opType#"_V2INT16";
908 let OperandType = opType#"_V2FP16";
919 let OperandType = opType#"_INT64";
924 let OperandType = opType#"_FP64";
930 let OperandType = opType#"_V2FP32";
936 let OperandType = opType#"_V2INT32";
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H A DSIInstrInfo.h761 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
765 return isInlineConstant(MO, OpInfo.OperandType); in isInlineConstant()
786 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType); in isInlineConstant()
803 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType); in isInlineConstant()
813 return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType); in isLiteralConstant()
874 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE); in getOpSize()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/
H A DWebAssemblyAsmTypeCheck.cpp246 if (Op.OperandType == MCOI::OPERAND_REGISTER) { in typeCheck()
255 assert(Op.OperandType == MCOI::OPERAND_REGISTER && "Register expected"); in typeCheck()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/
H A DDWARFDebugFrame.h500 enum OperandType { enum
514 static const char *operandTypeString(OperandType OT);
518 static ArrayRef<OperandType[MaxOperands]> getOperandTypes();
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp138 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in encodeReg()
199 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in encodeImm()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCTargetDesc.cpp101 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType == in evaluateBranch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp740 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
847 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); in fixupReg()
852 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type, in fixupReg()
861 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); in fixupReg()
1524 switch ((OperandType)Op.type) { in readOperands()
1891 OperandType type = (OperandType)operand.type; in translateImmediate()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp124 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != in evaluateBranch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td69 let OperandType = "OPERAND_MEMORY";
102 let OperandType = "OPERAND_MEMORY";
110 let OperandType = "OPERAND_MEMORY";
120 let OperandType = "OPERAND_MEMORY";
128 let OperandType = "OPERAND_MEMORY";
136 let OperandType = "OPERAND_MEMORY";
145 let OperandType = "OPERAND_MEMORY";
161 let OperandType = "OPERAND_MEMORY";
174 let OperandType = "OPERAND_PCREL";
181 let OperandType = "OPERAND_PCREL";
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