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Searched refs:OpNode (Results 1 – 25 of 38) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td21 SDPatternOperator OpNode,
26 def : Pat<(OpNode
31 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl),
36 def : Pat<(OpNode
41 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl),
54 SDPatternOperator OpNode,
57 defm : VectorBinaryArith<OpNode,
60 defm : VectorBinaryArith<OpNode,
H A DVEInstrInfo.td536 SDPatternOperator OpNode = null_frag,
568 SDPatternOperator OpNode = null_frag,
591 SDPatternOperator OpNode = null_frag,
607 SDPatternOperator OpNode = null_frag,
678 [(set Ty:$sx, (OpNode Ty:$sz))]>;
682 [(set Ty:$sx, (OpNode (Ty mimm:$sz)))]>;
768 [(set Tyo:$sx, (OpNode Tyi:$sy))]>;
1048 [(OpNode Ty:$sx, ADDRrri:$addr)]>;
1052 [(OpNode Ty:$sx, ADDRrii:$addr)]>;
1056 [(OpNode Ty:$sx, ADDRzri:$addr)]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
H A DNVPTXInstrInfo.td170 multiclass I3<string OpcStr, SDNode OpNode> {
219 multiclass F3<string OpcStr, SDNode OpNode> {
393 multiclass F2<string OpcStr, SDNode OpNode> {
510 multiclass ADD_SUB_i1<SDNode OpNode> {
1706 : ISET_FORMAT<OpNode, Mode,
1718 : ISET_FORMAT<OpNode, Mode,
2073 [(OpNode (i32 4))]>;
2076 [(OpNode (i32 5))]>;
2080 [(OpNode (i32 6))]>;
2084 [(OpNode (i32 7))]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td6719 asm, ".8b", OpNode, v8i8>;
8103 (OpNode (v4f16 V64:$Rn),
8130 (OpNode (v2f32 V64:$Rn),
8417 (OpNode (v4i16 V64:$Rn),
8430 (OpNode (v8i16 V128:$Rn),
8443 (OpNode (v2i32 V64:$Rn),
8455 (OpNode (v4i32 V128:$Rn),
8475 (OpNode FPR32Op:$Rn,
8491 (OpNode (v4i16 V64:$Rn),
8504 (OpNode (v8i16 V128:$Rn),
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td3983 def : Pat<(_.VT (OpNode _.RC:$src0,
3994 def : Pat<(_.VT (OpNode _.RC:$src0,
6216 (_.VT (OpNode
6225 (_.VT (OpNode
6416 (OpNode _.RC:$src2,
6505 (_.VT (OpNode _.RC:$src2,
7005 (OpNode _.RC:$src2,
8719 (OpNode (_.VT
9231 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
9255 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
[all …]
H A DX86InstrFMA.td179 SDPatternOperator OpNode,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
244 SDPatternOperator OpNode, RegisterClass RC,
247 x86memop, RC, OpNode, sched>;
249 x86memop, RC, OpNode, sched>;
251 x86memop, RC, OpNode, sched>;
405 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
482 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
509 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
[all …]
H A DX86InstrFPStack.td175 multiclass FPBinary_rr<SDPatternOperator OpNode> {
179 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
181 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
183 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
195 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
197 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
202 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
204 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
352 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
354 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
[all …]
H A DX86InstrXOP.td94 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
106 (vt128 (OpNode (vt128 VR128:$src1),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
140 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
261 (vt128 (OpNode (vt128 VR128:$src1),
267 def : Pat<(OpNode (load addr:$src2),
282 multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
289 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
[all …]
H A DX86InstrSSE.td30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
190 multiclass sse12_move_rr<SDNode OpNode, ValueType vt,
821 [(set DstRC:$dst, (OpNode SrcRC:$src))]>,
1811 [(set RC:$dst, (OpNode RC:$src1,
2079 (vt (OpNode RC:$src1,
2897 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3533 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3699 (vt128 (OpNode (memop addr:$src1),
7860 (vt128 (OpNode VR128:$src1,
7874 (vt256 (OpNode VR256:$src1,
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
328 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
333 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
339 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
366 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
481 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
492 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
509 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
1449 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
[all …]
H A DMipsInstrFPU.td112 SDPatternOperator OpNode= null_frag> :
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
121 SDPatternOperator OpNode = null_frag> {
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
137 SDPatternOperator OpNode = null_frag> :
146 SDPatternOperator OpNode= null_frag> {
203 SDPatternOperator OpNode = null_frag> :
210 SDPatternOperator OpNode = null_frag> :
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
259 SDPatternOperator OpNode = null_frag> :
[all …]
H A DMipsMSAInstrInfo.td1296 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1307 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1314 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1324 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1404 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1463 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1498 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
2313 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2660 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2667 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
[all …]
H A DMicroMipsDSPInstrInfo.td179 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
215 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
252 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
284 class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
291 class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
336 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
341 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
H A DMicroMipsInstrFPU.td14 SDPatternOperator OpNode = null_frag> {
15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
H A DMipsInstrInfo.td1315 SDPatternOperator OpNode = null_frag>:
1328 SDPatternOperator OpNode = null_frag> :
1382 SDPatternOperator OpNode = null_frag,
1395 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1398 SDPatternOperator OpNode = null_frag,
1410 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1427 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1434 SDPatternOperator OpNode= null_frag> :
1443 SDPatternOperator OpNode= null_frag> :
1453 SDPatternOperator OpNode= null_frag> :
[all …]
H A DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
H A DMicroMipsInstrInfo.td209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
295 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
303 SDPatternOperator OpNode = null_frag> :
317 SDPatternOperator OpNode = null_frag> :
320 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
335 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
345 SDPatternOperator OpNode, InstrItinClass Itin,
[all …]
H A DMips16InstrInfo.td1303 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1304 Mips16Pat<(OpNode CPU16Regs:$r),
1310 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1311 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1333 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1334 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1341 class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1342 Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
1358 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
411 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
621 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
692 string OpcStr, PatFrag OpNode>
710 string OpcStr, PatFrag OpNode>
797 [(set R0, (OpNode ADDRri:$addr, R0, GPR:$new))]> {
882 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td272 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
287 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
300 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
479 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
482 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
495 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
498 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
597 class StoreRR<string OpcString, PatFrag OpNode, ValueType Ty>
600 [(OpNode (Ty GPR:$Rd), ADDRrr:$dst)]>,
614 class StoreRI<string OpcString, PatFrag OpNode, ValueType Ty>
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2970 (OpNode (TyQ QPR:$src1),
2982 (OpNode (TyQ QPR:$src1),
2991 SDNode OpNode>
3065 (TyQ (OpNode (TyD DPR:$Vn),
3074 (TyQ (OpNode (TyD DPR:$Vn),
3446 SDNode OpNode> {
3701 SDNode OpNode> {
7398 : NEONFPPat<(f32 (OpNode SPR:$a)),
7442 : NEONFPPat<(f32 (OpNode GPR:$a)),
7450 : NEONFPPat<(i32 (OpNode SPR:$a)),
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td216 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
230 SDNode OpNode> {
239 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
242 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
251 SDNode OpNode> {
262 SDNode OpNode> {
271 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
294 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
296 [(OpNode immU6:$a)]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td327 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
333 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
361 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
366 [(set Ty:$dst, (OpNode ADDRri:$addr))],
372 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
382 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
383 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
403 [(OpNode Ty:$rd, ADDRrr:$addr)],
408 [(OpNode Ty:$rd, ADDRri:$addr)],
425 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td233 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
234 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
236 class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
237 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;

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