Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance
1587 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in selectDivRem() local1599 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectDivRem()1603 if (OpEntry.OpSignExtend) { in selectDivRem()1604 if (OpEntry.IsOpSigned) in selectDivRem()1606 TII.get(OpEntry.OpSignExtend)); in selectDivRem()1633 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) in selectDivRem()1645 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()1667 .addReg(OpEntry.DivRemResultReg); in selectDivRem()
1953 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1963 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1965 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1966 if (OpEntry.IsOpSigned) in X86SelectDivRem()1968 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1994 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()2006 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2024 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()