| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
681 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
726 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstSrcDstInstruction()
[all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5408 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
5410 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5412 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
5429 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5441 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5451 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
5472 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
5474 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5493 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5499 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2148 const T4 &Op4) {
2150 m_Argument<4>(Op4));
2157 const T4 &Op4, const T5 &Op5) {
2158 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3, Op4),
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1609 SDValue Op4 = Node->getOperand(4); in Select() local
1611 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1379 SDValue Op3, SDValue Op4);
1381 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 412 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
413 (inst $Op1, $Op2, $Op3, $Op4)>;
429 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
430 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
2083 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
2084 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2085 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
2086 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2087 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
2088 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5980 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
5988 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
5997 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6624 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
6625 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6629 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
6673 LastOp = &Op4; in tryConvertingToTwoOperandForm()
6694 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 8299 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
8300 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
8306 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
8307 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| H A D | LegalizeIntegerTypes.cpp | 1986 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4)); in PromoteIntOp_PREFETCH() local
1988 Op2, Op3, Op4), in PromoteIntOp_PREFETCH()
|