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Searched refs:Op1VT (Results 1 – 3 of 3) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14347 EVT Op1VT = N->getOperand(1).getValueType(); in combineStoreFPToInt() local
14355 (Op1VT == MVT::i32 || Op1VT == MVT::i64 || in combineStoreFPToInt()
14356 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14381 unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; in combineStoreFPToInt()
14384 DAG.getValueType(Op1VT) }; in combineStoreFPToInt()
14784 EVT Op1VT = N->getOperand(1).getValueType(); in PerformDAGCombine() local
14803 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
14819 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()
14824 if (Op1VT == MVT::i64) in PerformDAGCombine()
14858 if (Op1VT.isSimple()) { in PerformDAGCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8829 EVT Op1VT = V1.getValueType(); in LowerCONCAT_VECTORS_i1() local
8833 assert(Op1VT == Op2VT && "Operand types don't match!"); in LowerCONCAT_VECTORS_i1()
8839 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerCONCAT_VECTORS_i1()
8906 EVT Op1VT = V1.getValueType(); in LowerEXTRACT_SUBVECTOR() local
8915 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerEXTRACT_SUBVECTOR()
9328 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
9331 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
9333 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3816 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
3819 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
3821 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()