Home
last modified time | relevance | path

Searched refs:Op0VT (Results 1 – 2 of 2) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2124 EVT Op0VT = Op0.getValueType(); in LowerOperation() local
2129 if (Op0VT.isFixedLengthVector()) in LowerOperation()
2134 if (!Op0VT.isVector()) { in LowerOperation()
2135 auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
5085 EVT Op0VT = Op0.getValueType(); in ReplaceNodeResults() local
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12380 EVT Op0VT = A.getOperand(0).getValueType(); in performVecReduceAddCombine() local
12381 if (Op0VT != MVT::v8i8 && Op0VT != MVT::v16i8) in performVecReduceAddCombine()
12388 B = DAG.getConstant(1, DL, Op0VT); in performVecReduceAddCombine()
12393 DAG.getConstant(0, DL, Op0VT == MVT::v8i8 ? MVT::v2i32 : MVT::v4i32); in performVecReduceAddCombine()