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Searched refs:OffsetReg (Results 1 – 22 of 22) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp296 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
297 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitPrologue()
301 .addReg(OffsetReg); in emitPrologue()
348 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
349 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitEpilogue()
357 .addReg(OffsetReg); in emitEpilogue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h51 unsigned OffsetReg,
57 unsigned OffsetReg,
247 unsigned OffsetReg) const;
255 unsigned OffsetReg) const;
H A DR600InstrInfo.cpp1018 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1019 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1024 OffsetReg); in expandPostRAPseudo()
1032 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1033 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1039 OffsetReg); in expandPostRAPseudo()
1094 unsigned OffsetReg) const { in buildIndirectWrite()
1101 unsigned OffsetReg, in buildIndirectWrite() argument
1126 unsigned OffsetReg) const { in buildIndirectRead()
1133 unsigned OffsetReg, in buildIndirectRead() argument
[all …]
H A DAMDGPUCallLowering.cpp198 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
200 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
395 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
397 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
H A DSIRegisterInfo.cpp705 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
711 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
718 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
724 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
H A DAMDGPUInstructionSelector.cpp761 Register OffsetReg = MI.getOperand(2).getReg(); in selectG_SBFX_UBFX() local
776 .addReg(OffsetReg) in selectG_SBFX_UBFX()
3478 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSmrdSgpr() local
3479 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg) in selectSmrdSgpr()
3483 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); } in selectSmrdSgpr()
H A DAMDGPURegisterBankInfo.cpp1550 Register OffsetReg = MI.getOperand(FirstOpnd + 1).getReg(); in applyMappingBFE() local
1566 auto ShiftOffset = Signed ? B.buildAShr(S64, SrcReg, OffsetReg) in applyMappingBFE()
1567 : B.buildLShr(S64, SrcReg, OffsetReg); in applyMappingBFE()
1619 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp132 unsigned OffsetReg; member
178 return Mem.OffsetReg; in getMemOffsetReg()
618 Op->Mem.OffsetReg = 0; in MorphToMemImm()
626 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
630 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
642 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
H A DX86ISelLowering.cpp32354 unsigned OffsetReg = 0; in EmitVAARGWithCustomInserter() local
32408 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARGWithCustomInserter()
32409 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARGWithCustomInserter()
32419 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32430 assert(OffsetReg != 0); in EmitVAARGWithCustomInserter()
32450 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32460 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
32467 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
H A DARMCallLowering.cpp103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
H A DThumb2InstrInfo.cpp611 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
612 if (OffsetReg != 0) { in rewriteT2FrameIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp248 unsigned OffsetReg; member
339 return Mem.OffsetReg; in getMemOffsetReg()
528 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
537 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
549 Op->Mem.OffsetReg = 0; in MorphToMEMri()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp234 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
235 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
H A DMipsSEInstrInfo.cpp895 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
909 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
H A DMipsISelLowering.cpp2545 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2547 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2550 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp166 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
171 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
H A DHexagonISelLowering.cpp3139 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
3145 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp253 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
255 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
H A DAArch64InstructionSelector.cpp5412 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
5422 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
5455 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
5464 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
5469 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
5475 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp94 unsigned OffsetReg = 0; member in __anon37a1e6760111::AArch64FastISel::Address
120 OffsetReg = Reg; in setOffsetReg()
124 return OffsetReg; in getOffsetReg()