| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 219 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local 232 NewVT, 2*OldElts), in ExpandRes_EXTRACT_VECTOR_ELT() 239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT() 243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT() 376 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local 396 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
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| H A D | LegalizeVectorTypes.cpp | 302 NewVT, Op); in ScalarizeVecRes_BITCAST() 1992 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local 2050 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE() 2080 Output = DAG.getUNDEF(NewVT); in SplitVecRes_VECTOR_SHUFFLE() 4785 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST() 4802 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST() 5281 if (!NewVT.isVector()) { in GenWidenVectorLoads() 5287 if (NewVT == WidenVT) in GenWidenVectorLoads() 5294 SDValue UndefVal = DAG.getUNDEF(NewVT); in GenWidenVectorLoads() 5316 NewVTWidth = NewVT.getSizeInBits(); in GenWidenVectorLoads() [all …]
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| H A D | DAGCombiner.cpp | 4498 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS() 4502 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS() 4559 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU() 4563 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU() 4635 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitSMUL_LOHI() 4640 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI() 4678 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitUMUL_LOHI() 4683 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI() 16709 (NewVT.getStoreSizeInBits() != NewBW || in ReduceLoadOpStoreWidth() 21748 EVT NewVT; in visitINSERT_SUBVECTOR() local [all …]
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| H A D | TargetLowering.cpp | 229 EVT NewVT = VT; in findOptimalMemOpLowering() local 234 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering() 235 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering() 236 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering() 238 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering() 242 NewVT = MVT::f64; in findOptimalMemOpLowering() 249 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering() 250 if (NewVT == MVT::i8) in findOptimalMemOpLowering() 252 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering() 254 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering() [all …]
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| H A D | LegalizeDAG.cpp | 3005 EVT NewVT = in ExpandNode() local 3008 assert(NewVT.bitsEq(VT)); in ExpandNode() 3011 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode() 3012 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode() 3016 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode() 3032 VT = NewVT; in ExpandNode()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1130 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local 1131 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT() 1132 NewVT = EltTy; in getVectorTypeBreakdownMVT() 1133 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT() 1141 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() 1600 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local 1601 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown() 1602 NewVT = EltTy; in getVectorTypeBreakdown() 1603 IntermediateVT = NewVT; in getVectorTypeBreakdown() 1605 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 376 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local 377 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn() 386 LLT NewLLT(NewVT); in lowerReturn() 388 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn() 391 if (NewVT.isVector()) { in lowerReturn()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.h | 129 EVT NewVT) const override { in shouldReduceLoadWidth() argument
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 552 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local 561 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments() 592 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 323 EVT NewVT) const override;
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| H A D | HexagonISelLowering.cpp | 3576 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth() 3578 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 769 EVT NewVT) const { in shouldReduceLoadWidth() 771 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth() 774 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth() 3006 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local 3009 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine() 3057 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local 3063 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
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| H A D | R600ISelLowering.cpp | 1731 EVT NewVT = MVT::v4i32; in constBufferLoad() local 1734 NewVT = VT; in constBufferLoad() 1737 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in constBufferLoad()
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| H A D | SIISelLowering.cpp | 4920 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local 4921 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults() 4922 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults() 4924 EVT SelectVT = NewVT; in ReplaceNodeResults() 4925 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults() 4934 if (NewVT != SelectVT) in ReplaceNodeResults() 4935 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults() 6264 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local 6268 ResultTypes[0] = NewVT; in lowerImage() 10195 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local [all …]
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| H A D | AMDGPUISelDAGToDAG.cpp | 951 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local 952 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 1581 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local 1584 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst() 1585 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 570 EVT NewVT) const override;
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| H A D | AArch64ISelLowering.cpp | 3320 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local 3324 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT() 3591 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local 3593 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL() 11302 EVT NewVT) const { in shouldReduceLoadWidth() 11304 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth() 13671 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); in tryExtendDUPToExtractHigh() local 13675 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()), in tryExtendDUPToExtractHigh()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1279 EVT NewVT) const override;
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| H A D | X86ISelLowering.cpp | 9443 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local 9445 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp() 9446 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp() 13413 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local 13414 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement() 18540 V1 = DAG.getBitcast(NewVT, V1); in lowerVECTOR_SHUFFLE() 18541 V2 = DAG.getBitcast(NewVT, V2); in lowerVECTOR_SHUFFLE() 27312 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems); in LowerVectorCTLZ_AVX512CDI() local 27313 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) && in LowerVectorCTLZ_AVX512CDI() 29647 Op = DAG.getNode(ISD::CTPOP, DL, NewVT, Op); in LowerVectorCTPOP() [all …]
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| /freebsd-13.1/contrib/llvm-project/clang/lib/AST/ |
| H A D | Decl.cpp | 2574 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local 2575 if (!NewVT) in getTemplateInstantiationPattern() 2577 VarTemplate = NewVT; in getTemplateInstantiationPattern()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1550 EVT NewVT) const { in shouldReduceLoadWidth() argument 1553 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2048 MVT NewVT = in expandUnalignedRVVLoad() local 2050 assert(NewVT.isValid() && in expandUnalignedRVVLoad() 2052 SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(), in expandUnalignedRVVLoad() 2079 MVT NewVT = in expandUnalignedRVVStore() local 2081 assert(NewVT.isValid() && in expandUnalignedRVVStore() 2083 StoredVal = DAG.getBitcast(NewVT, StoredVal); in expandUnalignedRVVStore()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8315 EVT NewVT = getVectorTyFromPredicateVector(VT); in PromoteMVEPredVector() local 8333 return DAG.getNode(ISD::BITCAST, dl, NewVT, PredAsVector); in PromoteMVEPredVector() 8364 EVT NewVT = PredAsVector.getValueType(); in LowerVECTOR_SHUFFLE_i1() local 8367 SDValue Shuffled = DAG.getVectorShuffle(NewVT, dl, PredAsVector, in LowerVECTOR_SHUFFLE_i1() 8368 DAG.getUNDEF(NewVT), ShuffleMask); in LowerVECTOR_SHUFFLE_i1() 8855 EVT NewVT = NewV.getValueType(); in LowerCONCAT_VECTORS_i1() local 8857 for (unsigned i = 0, e = NewVT.getVectorNumElements(); i < e; i++, j++) { in LowerCONCAT_VECTORS_i1() 9154 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local 9156 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13728 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation() local 13729 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops); in combineElementTruncationToVectorTruncation()
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