| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 159 Instruction *Ret = NewShift; in reassociateShiftAmtsOfTwoSameDirectionShifts()
161 Builder.Insert(NewShift); in reassociateShiftAmtsOfTwoSameDirectionShifts()
320 return NewShift; in dropRedundantMaskingOfLeftShiftInput()
322 Builder.Insert(NewShift); in dropRedundantMaskingOfLeftShiftInput()
397 if (auto *NewShift = cast_or_null<Instruction>( in commonShiftTransforms() local
399 return NewShift; in commonShiftTransforms()
816 Value *NewShift = in FoldShiftByConstant() local
818 NewShift->takeName(Op0BO); in FoldShiftByConstant()
834 NewShift->takeName(Op0BO); in FoldShiftByConstant()
860 Value *NewShift = in FoldShiftByConstant() local
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| H A D | InstCombineCompares.cpp | 1731 Value *NewShift = in foldICmpAndShift() local
1736 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift); in foldICmpAndShift()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3206 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine() local
3210 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3230 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
3233 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3240 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
3242 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3291 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine() local
3293 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1927 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask() local
1936 insertDAGNode(DAG, N, NewShift); in foldMaskedShiftToScaledMask()
1937 DAG.ReplaceAllUsesWith(N, NewShift); in foldMaskedShiftToScaledMask()
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| H A D | X86ISelLowering.cpp | 39293 SDValue NewShift = TLO.DAG.getNode( in SimplifyDemandedBitsForTargetNode() local
39296 return TLO.CombineTo(Op, NewShift); in SimplifyDemandedBitsForTargetNode()
43784 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical() local
43785 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask); in combineShiftRightLogical()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2241 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt); in foldAddSubOfSignBit() local
2245 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); in foldAddSubOfSignBit()
8114 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant() local
8116 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
8825 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
8827 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); in visitSRL()
8835 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
8840 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 16296 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1, in PerformLongShiftCombine() local
16298 DAG.ReplaceAllUsesWith(N, NewShift.getNode()); in PerformLongShiftCombine()
16299 return NewShift; in PerformLongShiftCombine()
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