Searched refs:MinPos (Results 1 – 2 of 2) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1809 unsigned MinPos = 0; in moveLowLatencies() local
1819 if (PredPos >= MinPos) in moveLowLatencies()
1820 MinPos = PredPos + 1; in moveLowLatencies()
1827 if (BestPos < MinPos) in moveLowLatencies()
1828 BestPos = MinPos; in moveLowLatencies()
1856 if (MinPos < i) { in moveLowLatencies()
1857 for (unsigned u = i; u > MinPos; --u) { in moveLowLatencies()
1861 ScheduledSUnits[MinPos] = SU->NodeNum; in moveLowLatencies()
1862 ScheduledSUnitsInv[SU->NodeNum] = MinPos; in moveLowLatencies()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40532 SDValue MinPos = Src; in combineMinMaxReduction() local
40537 std::tie(Lo, Hi) = splitVector(MinPos, DAG, DL); in combineMinMaxReduction()
40539 MinPos = DAG.getNode(BinOp, DL, SrcVT, Lo, Hi); in combineMinMaxReduction()
40557 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos); in combineMinMaxReduction()
40565 SrcVT, DL, MinPos, DAG.getConstant(0, DL, MVT::v16i8), in combineMinMaxReduction()
40567 MinPos = DAG.getNode(ISD::UMIN, DL, SrcVT, MinPos, Upper); in combineMinMaxReduction()
40571 MinPos = DAG.getBitcast(MVT::v8i16, MinPos); in combineMinMaxReduction()
40572 MinPos = DAG.getNode(X86ISD::PHMINPOS, DL, MVT::v8i16, MinPos); in combineMinMaxReduction()
40573 MinPos = DAG.getBitcast(SrcVT, MinPos); in combineMinMaxReduction()
40576 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos); in combineMinMaxReduction()
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