Searched refs:MidVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 4355 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt); in getPromotedVectorElementType() local 4356 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType() 4357 return MidVT; in getPromotedVectorElementType() 4768 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4801 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4802 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() 4822 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode() 4848 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() 4859 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode() 4891 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode() [all …]
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| H A D | LegalizeFloatTypes.cpp | 530 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local 535 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3359 EVT MidVT = VT.isVector() ? in performTruncateCombine() local 3363 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout()); in performTruncateCombine() 3364 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine() 3373 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13481 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local 13482 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine() 13487 MidVT, dl, in performConcatVectorsCombine() 13488 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine() 13489 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 45547 EVT MidVT = VT.changeVectorElementType(MVT::i16); in combineTruncateWithSat() local 45548 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()
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